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High Speed Serial — Differential Pairs Done Right

After years of pooh-poohing AMD, Intel had to admit you could get more data throughput switching to a high-speed serial approach. Let’s say high-speed serial is in the 1 to 10 Gbps range per lane, and use PCIe as an example. This is where the benefits become irresistible and the behavior becomes unexpected according to the previous rules of layout design.

The PCIe specification helps define the different pieces of a general high-speed solution when it breaks down the interface into the transmitter, receiver, and channel. Much of the benefit from high-speed-serial comes from the transmitter pre-emphasis, receiver equalization and packet management. But once you are in layout, the design challenges are all in the channel. The copper routes and surrounding physical structures all effect how the high-speed signals propagate. This sounds like an RF design for good reason — as the speeds increase, trace geometry and surrounding materials contribute to channel characteristics as if they were discrete components, and discretes don’t display the reactive behavior you expected. This is where the schematic tells the intended behavior. Only after the layout is done is the design showing real electrical behavior.

Once you have your RF hat on and are looking at the layout as part of the whole design, the required design disciplines make sense. The first part of the design solution is setting up a routing physical environment. This is a 3-D design of all the right materials and plane arrangement around a high-speed routing channel. The performance and modeling of a high-speed differential pair starts with a very narrowly defined routing environment — surrounding material, planes, and geometries. Generally speaking, we build the board structure around the channel and that justifies making the assumptions behind a classic strip-line topology. This means we already have a plan for the board’s connectors, layer use, and general physical arrangement. Ensuring this routing channel setup is established first, and stays in place must be established before routing.

The other common killer assumption is that power and ground are golden. As design speeds’ edge rates exceed the traditional discrete component frequency behavior, the stable power assumption falls apart and the power distribution network (PDN) becomes part of the SI design. Your transmitter buffer output model assumes good power across the whole frequency spectrum. So, before it is even worth the time to start routing a high-speed differential pair, a solid PDN must be in place for the transmitters. There are two good ways to ensure this prerequisite is met: massive overdesign or power integrity (PI) simulation. I must admit I’ve done both, but recommend simulation.

Now that your routing environment is established, the point-to-point topology of a high speed pair would at first seem like the route would be boring, but the fun part of high-speed layout starts here by making this route a high quality transmission line. The two main things to keep in mind now are keeping the phases matched and keeping the characteristic impedance matched.

The difference in phase of each leg of a differential pair comes from pin fanouts, different propagation speeds on different layers, and different structures, such as vias. The routing tool can keep the lengths matched along the way, but it is up to you to ensure the transition from the channel to the chips also keeps the electrical lengths matched and to avoid unbalanced copper structures. With all those considerations taken care of, laying down the route is all about the characteristic impedance. Antipads, stripping out non-functional pads, teardrops, and rounding are all high-speed features striving toward the same goal — matched and unchanging characteristic impedance. Since all of the copper in all three dimensions contribute to the characteristic impedance, every copper detail is part of the electrical design.

These details needed for success are electrical constraints of physical design. The path to success is to enter these constraints as layout rules and allow dynamic recalculation as the physical design work progresses. The visibility that you are still on the path to success is simulation. Until you have years of RF design experience some of the things that change your characteristic impedance are not obvious, so a post route SI simulation is at least as important as a SPICE simulation of an analog filter.

Do you have a favorite reference design you use as a starting point? Please leave it below.


RF, PCI Express

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Comments 1

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Randall, Thank you for the thought-provoking article! I appreciate the reiteration about the importance of simulation post-layout. Many times, a post-layout review catches issues to which the designer was blind during routing. Furthermore, this would allow all boards and the backplane in a system to pass a commonly coordinated checklist regarding trace width and spacing strategy to avoid issues around engineer's perogative vs top-down coordination. Thnks again for the article!

7:46 AM Feb 11, 2013

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