Since FPGAs, field programmable gate arrays, are in their very nature fluid and changing, how do you force them into your electronics design techniques that all assume fixed parts? Hardware design uses, well… hardware, physical chips and resistors that have fixed functionality. We pull parts from libraries, wire them up, lay etch and build the gizmo. FPGAs throw out the definition of hardware and mess up that design flow from libraries to schematic to PCB layout, but their flexibility is worth the trouble. There are two main sticking points, parts for a schematic and connections for the layout.
FPGAs’ hundreds of user pins show up on several to dozens of schematic symbols to place an FPGA on a schematic. Normally a librarian would build up a set of symbols with helpful pin names, like “Data.” But as the FPGA functionality changes with each compile, that plan won’t work. So the options are to keep the pins not-locked-down, or make all the symbols very generic, “Bank 2 IO_23.” I was just in Texas negotiating a truce between two different design centers who took different sides of this debate. As long as your tools are powerful enough to accommodate all the nuances, both the librarians and the FPGA schematic designers can peacefully coexist. Which is another reason to buy I/O Designer to tie the disparate tools together with automation.
Assuming you plowed through to the layout, now the layout designer has two problems. His connections are all scrambled into a knot like no one planned out the chip, and they keep changing. The root of these problems is the same, the decision on what signal goes on which pin is done entirely by the FPGA compiler with little regard to the physical design. An experienced designer can improve on that and there are some Xilinx tool features to facilitate the FPGA designer who cares. But there is also a uniquely qualified design option in Expedition I mentioned earlier, I/O Designer. This little FPGA gem can remember the FPGA pin capability rules while looking at the physical layout orientations and connections. It unravels the connections turning a layout nightmare into an orderly set of parallel lines.
I’ve found using all the Expedition tools I can relieves most of the headaches caused by FPGAs. How do you deal with trying to design with a part that keeps changing?