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Introducing Aspen

You may have noticed many of the demo graphics used are new to the 7.9.4 release.  The Aspen demo was designed to showcase the Expedition Enterprise flow starting with DxDesigner and I/O Designer and continuing through Expedition XtremePCB and Valor.  On November 13, in my webinar on concurrent engineering I will feature Aspen and how the Mentor Technical Marketing team used the integrated concurrent Expedition Enterprise PCB design software.

What is a concurrent enabled flow?  In the Mentor Graphics PCB Expedition design environment with  concurrent licensing and setup, multiple engineers can work on the same project, including the schematic, constraint rules and PCB layout at the same time.  All versions of the Expedition Enterprise DxDesigner are capable of concurrent editing of a schematic project.   At our office in Colorado, Aspen was created concurrently with 4 engineers working on the schematic, 3 on the CES rules, and 4 working on the Expedition XtremePCB layout all at the same time!

Aspen features three Altera FPGA’s, DDR2 and DDR3 memory, PCI Express, and switching power supply generation.  The FPGA design was generated by reading a Verilog source file, and pins were assigned to top level symbol checked for compatibility with the appropriate signal bank.  Bank level symbols were created automatically by I/O Designer and the schematic blocks in DxDesigner were automatically created and linked in the project to I/O Designer.  With the power of I/O Designer, the FPGA engineer does not need to spend hours attempting to tediously unscramble the nets from the FPGA to the child devices.  The tool optimizes your net routing with its complex unraveling algorithms and was used to unravel and optimize the Aspen design.

I’ve also used the Aspen design to demonstrate the new features introduced in DxDesigner.  You can also use this demo design to try the new features yourself and explore the possibilities.  The demo is available in our virtual lab which uses the ASPEN database to showcase the new features included with DxDesigner 7.9.4 for Expedition Enterprise.  The lab should take about an hour to complete and will give you an overview of the new technology and features in DxDesigner.

Over the next few months I will expand on many of these new features, and answers to “How did you do this?” in their own unique blog posts.  Subscribe to this feed to stay informed!

Gary Lameris
Mentor Graphics, Technical Marketing Engineer
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Gary Lameris joined Mentor Graphics in 2008 as a Technical Marketing Engineer for the Mentor Expedition PCB flow.  Prior to Mentor Graphics, he has served on the DxDesigner and PADS Customer Advisory Boards, and is the founder and manager of the DxDesigner Yahoo forum. Throughout his career, Gary has served on the boards of a variety of associations, including; chairing the Associate Membership Committee for the National Conference on Weights and Measures, serving on the weighing subcommittee of the National Type Evaluation Technical Committees (NTETC), and acting as industry advisor to the National Institute of Standards and Technology (NIST). His experience includes 22 years as a Senior Design Engineer at Hobart Corporation and Program Manager at Simclar Inc., a contract assembler of printed circuit boards. Gary has a BSEE from Michigan Technological University.

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Gary LamerisMentor Graphics Technical Marketing Engineer focusing on DxDesigner for Expedition Enterprise and PADS PCB layout Visit PCB Schematic Design with DxDesigner

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