Whether you are trying to correlate simulated waveforms to measured waveforms for a DDR3 signal, or board timing numbers for a simple SDRAM bus, or measured Z-parameters when looking at a PDN impedance, or even just a simple trace impedance measurement on the TDR, it all begins with the proper stackup. I explore some of the commonly overlooked nuances of stackup modeling in my recent article in InCompliance magazine: http://www.incompliancemag.com/index.php?option=com_content&view=article&id=762:making-real-boards&catid=26:design&Itemid=130.
In the article, I look at a number of factors, the most important of which being the dielectric constant. And that is true not only for simple impedance modeling, but also for timing and general SI and PI as well. The HyperLynx engineering team spends an amazing amount of time and energy ensuring that our electromagnetic modeling and circuit simulation produce incredibly accurate results, but it is all for nought if the board parameters are not properly modeled. My article discusses dielectric modeling, its variance for different dielectric heights and around the traces, as well as modeling of the traces themselves.
The article is mainly focused on impedance, but the same truths apply to general SI and PI as well. One item I do not discuss is loss, but HyperLynx uses a multi-pole deBye model for loss which ensures accuracy for your SERDES simulations, as well as allowing for surface roughness which is important for signals above 5GHz.
If you take the time to talk to your board manufacturer and make sure you understand your board parameters properly, you will end up with simulation results that correlate to your measurement, and an excellent understanding of how your board will perform before you even make the first prototype.