When trying to design SERDES signals on board, designers often receive recommendations on placing stitching vias around differential signal vias of a channel. The purpose is to provide continuous return current path when signals switch layers, so that the discontinuity of trace impedance can be minimized.
Because of the increasing board density, the issues designers are facing by following this recommendation are how many to use and where to place these stitching vias. Some people decide to be on the conservative side and put at least 2 stitching vias around every differential signal via pair that carries signals with data rates over 1Gbps; some do not follow the guideline at all and include no stitching vias for any multi-Gbps signals. Regarding the locations of stitching vias, some designers leave stitching vias wherever there is room for them; while some pay attention to make sure stitching vias are placed in the vicinity of designated signal vias.
With all these different design practices, some boards are over designed which results in higher product costs; some boards see failed SERDES signals.
To avoid design problems and maintain cost budget, designers need to understand the effects of stitching vias. The knowledge and design rules can be obtained by performing 3D analysis to signal vias with stitching.
In general, stitching vias need to be placed close to the signal vias: stitching vias far away from the signal vias waste board space and will not help provide continuous return path. In addition, not all SERDES signal need to have stitching vias; in many cases, using 2 stitching vias for one differential signal via pair is enough.
Read this article to get all the details on stitching via effects and the related design considerations.