IPC-7351 for SMT technology defines the rules for creating optimized land pattern CAD library parts using a 3-Tier system – Least (high density), Nominal (controlled environment) and Most (ruggedized & shock resistant). Many PCB designers and CAD Librarians have heard about the IPC-7351B standard, but few people know how they work. The IPC LP Calculator has made life easy for the PCB design industry by automatically generating accurate land pattern data derived from component dimensions. Part 7 of this series will describe the basic fundamental aspects of defining the optimized land (pad) size for a CAD library part and the mathematical model of the LP Calculator.
Land (Pad) Size and Location:
These 7 factors are used to calculate the optimum Land Size –
Component Body Tolerance
Component Terminal Tolerance
Land Size Round-off
Land Spacing Round-off
Solder Joint Goals for Toe, Heel and Side
The Fabrication (Manufacturing) Tolerance compensates for the fabrication allowance for etch back. By adding a fabrication tolerance, we calculate the land area that we need after the fabrication etching process. If your manufacturer over-sizes the land areas during the CAM process to compensate for their own etching tolerances, this is referred to as “double tolerance” because of double compensation for the same allowance. Ask your manufacturer if they over-size the land features. If they do, tell them that you already compensated for that in your CAD library. The IPC-7351 fabrication tolerance is 0.05mm.
The Placement (Assembly) Tolerance compensates for the pick and place machine accuracy. When parts are manually placed or machine placed, there is a small margin of placement accuracy that must be accounted for. The IPC-7351 assembly tolerance is 0.05mm.
Land Place (Spacing) Round-off relates to the land center to land center spacing. The goal in the IPC-7351 is to place all lands on a 0.05mm grid, so the space between the land span is rounded to 0.1mm increments so that the distance from the center of the land pattern to the center of the land is in 0.05mm increments. This plays a critical role in trace routing to achieve the highest packing density. In this picture example of a common Chip Component, the land snap grid is 0.05 mm from the center of the part to the center of the lands. The C1 & C2 dimensions.
Land Size Round-off is the value that the land size rounds up or down to. The IPC-7×51 standards round land sizes to 0.05mm increments with the exception of micro-miniature component packages that are typically less than 1.6mm in size. The micro-miniature part land size round-off is set to 0.01mm increments. In the picture above, the “X” & “Y” dimensions are rounded off in 0.05 mm increments. Even the land corner radius is rounded in 0.05 mm increments.
Solder Joint Goals for Toe are usually the outside the component lead with two exceptions, the J-Lead and the Molded Body components the Toe is under the component body. The Heel goals are normally on the inside of the component lead and the side goals are for both sides of the component lead. In Part 5 of this series I listed the component Lead Forms. Every lead form has it’s unique solder joint goal table. Here is a sample table for the Least, Nominal and Most “Toe, Heel and Side” goals and the Placement Courtyard Excess for the Gull Wing component family. Notice the Round-off factor is in 0.05 mm increments.
When all of the Tolerances, Round-offs and Solder Joint goals are applied the end result is a perfect land pattern.
If all the Tolerances and Solder Joint Goals were removed from the mathematical model, the component lead would be equal to the land size. This is the starting point for all land size calculations. The picture below illustrates a Chip Component (black) without Tolerances, Round-offs, or Solder Joint Goals and the land size (cyan).
The resulting solder joint for a chip component should look similar to this picture. Note that the component terminal never touches the land. There must be solder paste between the component lead and the land to form the best solder joint. Here’s a note from the IPC J-STD-001D “Requirements for Soldered Electrical and Electronic Assemblies”. Section 4.14 Solder Connection: All solder connections shall indicate evidence of wetting and adherence where the solder blends to the solder surface.