Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed. And I mean that more figuratively than literally. Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds. That is where a complement of pre-layout and post-layout signal integrity simulation can help.
Take a look at this article discussing the differences: http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640
Pre-layout simulations are a great way to see if a design is even feasible. For instance, if you are trying to run a 6Gbps link like Serial ATA or SAS through several boards and a long backplane, it might not make it unless you make the appropriate choice of connector, board stackup, and trace geometries. Pre-layout simulation is a great way of gaining an understanding of the limitations of a certain bus architecture, and understanding the margins of your system. This opens your eyes to what your design is actually doing. It also leads to a better understanding of what might be a potential problem once the system is built. In fact, post-layout simulation is even more useful in that regard, as it gives the most accurate view of what is going on at the receiver. Post-layout simulation is often more useful than actual measurement. Multi-GHz busses cannot be measured while they are running; they usually need to be measured into some sort of test fixture. So, having a post-layout simulation handy to see what is going on in the actual design, including the effects of equalization at the receiver, is invaluable.