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Shorter stubs are getting longer

…It all depends on how fast you are trying to go.  That’s really the name of the game with anything signal integrity.  The faster we go, the more “new” problems we face.  Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal.
At the beginning of my career, I worked a bunch on a bus called SCSI.  Up to 15 hard drives all connected together on the same bus, each hard drive connection having around a 1″ stub (sometimes more).  Luckily the fastest it went was 80MHz, but it was still a challenge from a signal integrity standpoint.  Fortunately SCSI, like many other parallel busses, has been replaced by a newer SERDES architecture.  SAS, or Serial Attached SCSI, is a lot easier to implement than its parallel predecessor, but presents some new challenges.  No need to worry about 1″ stubs any more on the hard drives, but now layer transitions and vias actually pose the threat of stubs.  For instance, on a 100-mil thick board, if you transition from the top layer to a middle layer using a traditional thru-hole via, the rest of that via will be acting like a stub, with a length on the order of 50 mils.  This can severely degrade the signal, and should be modeled in simulation before creating the board design to ensure it is not overly detrimental.  Depending on the speed, the via and its stub may require a model from a 3D field solver, which can be created in HyperLynx 8.2.  To learn more about this and other aspects of via design, check out my recent article in PCDandF:
http://pcdandf.com/cms/component/content/article/171-current-issue/8439-designers-notebook

SERDES

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About Patrick Carrier

Patrick CarrierPatrick Carrier is a Product Marketing Manager for PCB analysis tools, including signal integrity, power integrity, electromagnetic compatibility, and thermal analysis. Visit The HyperBlog

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