Yeah, I can totally see Homer Simpson designing his SERDES bus and getting frustrated by all the additional insertion loss caused by his vias, and muttering to himself, “Stupid vias…” and grumbling. And then going into the lab, looking at his failing eye diagram, and shouting “D’oh!”. Okay, well Homer Simpson probably won’t be designing any SERDES busses anytime soon. But anyone doing so would probably mimic his frustration.
But, there is a way to conquer those “stupid vias” by designing “smart vias”. That was actually the title of a recent article in Printed Circuit Board Design and Fabrication magazine: http://pcdandf.com/cms/component/content/article/171-current-issue/8439-designers-notebook
The key is understanding how to make the vias look like the rest of the channel. And whether you are designing a SERDES bus like PCI Express or a fast single-ended bus like DDR2 or DDR3, accomplishing that task of making “smart vias” requires different design changes. For instance, with a SERDES bus like PCI Express, you will be mostly concerned with the size and shape of the vias, and editing properties like drill size, pad size, and antipad size. You will also want to minimize stubs. But with a fast single-ended bus like DDR3, you will be more concerned with the placement of nearby stitching vias and/or stitching capacitors. You can easily simulate and identify those design tradeoffs in HyperLynx.