Yes, you should care about the fact that PCB traces, when actually manufactured, end up having more of a trapezoidal shape. This is especially true when modeling those traces to determine the correct impedance. More important than the trapezoid shape itself is the resulting change in trace width. Typically, on 1/2-oz. copper, the etching process leaves the top of a trace about 0.5 mils narrower than the bottom of the trace. That means that a 5-mil trace is actually 4.5-mils wide on top. So, when modeling traces to determine impedance, such as in the Stackup Editor in HyperLynx, it is best to take this into account by using the mean trace width. For a 5-mil trace, that would mean using 4.75 mils as the trace width, since it will be 5 mils at the base and 4.5 mils on top.
The proper modeling of trace width is vital to ensuring your impedance calculations match what is actually being manufactured. Proper dielectric modeling is also important – not only to make sure you are using the right dielectric constant values (as discussed in yesterday’s blog post) – but also in the area around the traces. Typically the area around the traces is more resin-rich, and will thus have a lower dielectric constant than the rest of the dielectric layer. You can model this in the the HyperLynx Stackup Editor by specifying a different dielectric constant for the trace layers.
You can read more about matching impedance calculations to measurement in my recent article in InCompliance magazine: