Simulating DDRx Designs - HyperLynx DDRx
DDRx memory interfaces are ubiquitous in today’s designs, yet validating them is surprisingly complex, requiring thousands of simulations and waveform measurements.
Would you like to know what your real DDRx design margins are and have a chance to improve them before you release your next board?
This seminar will explain how to use Mentor Graphics’ market-leading HyperLynx solutions to address the challenges of DDRx designs .
This will include:
- a review of classic signal integrity analysis using HyperLynx LineSim for simulations of interconnect technologies
- addressing post-route PCB verification techniques using HyperLynx BoardSim
- designing for validation for DDRx-Designs
- an introduction to HyperLynx Power Integrity, discussing AC analysis and decoupling capacitor strategies as well as DC Drop.
What You Will Learn
- Create and simulate LineSim free-form schematics
- Investigate stack-up strategies , termination strategies and crosstalk issues
- Identify and debug SI issues for different classes of DDRx signals
- Run BoardSim simulation interactively and in batch mode
- Setup and veryfication of DDRx based memory system by using DDRx wizard both for memory on board and for multiboard configurations
- AC analysis and decoupling capacitors strategies as well as identification of excessive voltage drop and high current density using DC Drop analysis
About the Presenter
Steve Gascoigne received his EE in Electronics from Exeter University. He has 25 years in the electronics industry, including 14 years as a hardware engineer and PCB designer at Plessey and Nortel networks, and 11 years as a field applications engineer.
Who Should Attend
- PCB Engineers/Designers
- Project and Engineering Managers
- FPGA/ASIC engineers
- Educational Researchers / Research post-graduates
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