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Expedition Technology Day



With growing number of large pin-count devices, shrinking BGA pin pitches, pre and post layout signal & power integrity analysis requirements and implementation of complex high speed constraints (DDRx, SATA, PCI Express, etc) for layout, design cycle time for dense, complex PCBs are not only delayed but also become unpredictable. Learn how Expedition Enterprise from Mentor Graphics can shorten your design cycles and make them more predictable so you can meet aggressive product launch windows and maximize profitability.

Expedition Enterprise from Mentor Graphics is the industry's most innovative PCB design flow, providing integration from system design definition to manufacturing execution. Its unique, patented technologies can reduce design cycles by 50 percent or more while significantly improving overall quality and resource efficiency.

What You Will Learn

  • Constraint-enabled high-speed layout: How signal integrity could be improved by improving routing
  • Accelerate PCB design cycle time: Collaborative design in a high-speed environment
  • Solve potential EMI, SI and PI problems: Finding critical electrical problems in massive post-route designs
  • DFM/DFF sign-off: Design rules checking for manufacturing success

Who Should Attend

Managers and engineers looking for best-in-class, integrated system design creation tools which enable:

  • Creation of constraint-enabled schematics
  • Optimized IO's for PCB design
  • Signal/power integrity analysis-based PCB layout and routing
  • Accelerate PCB design cycle times with concurrent layout and high-speed constraint entry
  • Implementation of industry-standard Valor DFM rules concurrently during the design flow to reduce revisions and costly re-spins of fab and assembly.


Expedition Technology Day, Fremont, CA

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