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Low-Risk, High-Confidence Design of High-Speed PCBs: Getting it Right the First Time

Overview

High speed PCB design practices are quickly evolving to better handle the rampant use of fast edge rate parts, rapidly increasing layer counts, higher power demands, and collapsing time to market windows. Getting the PCB design right the first time has become the exception. Seminar attendees will be introduced to new HyperLynx based high speed design analysis techniques aimed at overcoming the design challenges of today’s performance-drive PCB designs.

What You Will Learn

  • An introduction to new HyperLynx based high speed design analysis techniques
  • New techniques to overcome today's design challanges

About the Presenters

Presenter Image Taylor Shull

Taylor Shull has been an Application Engineer at Mentor Graphics for 12 years. He has worked with many customers to solve signal and power integrity issues, from simple approaches to complex multi-giga bit SERDES designs. More recently, Taylor has been focused on helping customers understand power delivery systems and how to solve the complex design challenges companies face. Taylor received his BSEE from Washington State University in 1996.

Presenter Image Chuck Ferry

Chuck Ferry is a product marketing manager for high-speed tools at Mentor Graphics. Focused on product definition for innovative industry-leading signal and power integrity solutions, Chuck has spent the last 12 years tackling a broad range of high-speed digital design challenges, spanning from system-level mother-board design to multi-gigabit channel analysis to developing and incorporating detailed characterizations of the IC, packages, connectors, and multiple boards.

Agenda

9:15-9:30: Welcome note.

9:30-10:15: Keynote:
Designing SERDES Links with Confidence: Modeling, Simulation, and Measurement of a 12.5-Gbps Channel

10:15-10.20: short break

10:20-11.20: HyperLynx overview

The Need for Speed and Accuracy: Techniques and Tools for Modern Signal-Integrity Analysis

11.20-12.20: Lunch and networking

12:20-1:05: DDRx Analysis

Analyzing DDR2/3/4 Memory Interfaces: Guarantee Your Margins Before You Build and Ship Boards

1:05-1:15: Break

1:15-2:00: Fast Whole-Board Verification

Using Accelerated Techniques to Exhaustively Scan Whole PCBs for Potential Problems

2:00-2.15: Break

2.15-3.00: Power Integrity Analysis

Design of Power-Distribution Networks in the Era of Proliferating Voltage Levels and High Current Demands

3:00-3.45: Break

3:45-4.30: 3-D Electromagnetic Analysis

Modeling Signal Discontinuities in SERDES Channels: Minding the Details without Breaking a Sweat

4.30-4.45: Wrap-up and lottery

Related Resources

 
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