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Are Complex PCB Layout Topologies Slowing You Down?



Remember the good old days of connecting the dots? With a bit of common sense and a correct netlist, laying out your board was a snap – heck, even autorouters did a decent job.

Things have gotten a lot more exciting lately, with parallel SERDES interfaces, hierarchical constraints, matched groups, and “virtual pins.” Combined with ridiculous timing margins and lower voltages, now you also have to deal with associated crosstalk and miniscule tolerances.

If there were only a handful of nets, it wouldn’t be so bad – the human brain could deal with that – but when 80 percent or more of your nets are high-speed, some layout tools should come with a supply of aspirin!

This session will show you how you can avoid the aspirin, using Xpedition Enterprise to easily define topologies in the form of constraints, verify that you got them right, and then lay out your board for right-the-first-time results.

What You Will Learn

  • PCB constraint types for high-performance designs
  • Methodology for efficient definition of constraints, then adherence while routing
  • Time, quality and performance benefits of constraint-driven high-speed PCB design

About the Presenters

Presenter Image Steve Herbstman

Steve Herbstman has more than 25 years experience in PCB Design. In addition to his design work, he was President of the Veribest (VBUG) users group for four years and Vice-Chair of the Mentor Users Group (MUG) for an additional year prior to joining Mentor Graphics. He is currently a Technical Marketing Engineer for the Board systems division.

Presenter Image David Wiens

David Wiens has over 20 years of experience in the EDA industry and is currently a product manager for the Systems Design Division of Mentor Graphics Corp. He joined Mentor Graphics in 1999 and previously held various engineering, marketing and management positions within the EDA industry. His focus areas have included advanced packaging, high-speed design, routing technology and integrated systems design.

Who Should View

  • PCB design managers looking to improve engineering/layout collaboration
  • PCB designers seeking to improve their productivity when dealing with high-speed PCB constraints
  • PCB engineers wanting to understand how their design intent can be communicated and implemented by PCB designers

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