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Enterprise-level FPGA-on-Board Optimization Strategies

Details

Overview

This session will present details of this flow along with a demonstration of pin optimization technology in the enterprise environment.

As FPGA on PCB implementations increase in complexity through utilization of 1000+ pin BGA packages with hundreds of programmable user I/O's, the challenges of effective I/O management in an enterprise environment continue to magnify.

Despite the use of EDA tools for FPGA design, schematic creation, and PCB layout, fixed pin assignment methods to manually created symbols and schematics persist, negating possible user I/O optimization, resulting in additional delays and manufacturing costs. Xpedition customers who have implemented pin optimization technology streamlined into a component management and design flow have realized schedule and cost benefits repeatedly throughout the enterprise.

What You Will Learn

  • How to quickly generate large FPGA (1000+ pin) fractured symbols in a component managed environment
  • How to automatically wire hundreds of nets on existing flat or hierarchical schematics
  • Management of ECO process across pin swaps
  • Automated pin optimization technology to untangle pin assignments to critical PCB interface components/connectors and between multiple FPGAs

About the Presenter

Presenter Image Frank Smetana

Frank is currently managing market development for FPGA-on-PCB Solutions. Frank originally worked at Mentor Graphics as a Field Applications Engineer for eight years supporting implementations at printed circuit board customer sites. He has also has been involved in customer ASIC and FPGA implementations through account management roles at Synopsys and Synplicity. Frank holds a BSEE from the University of Illinois at Urbana-Champaign and an MSEE from the Illinois Institute of Technology.

Who Should View

  • Engineering managers
  • FPGA designers
  • PCB designers
  • Project managers

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