IC Package Design Optimization and Analysis for USB 3.0
On-demand Web Seminar
This webinar will discuss IC Package design for USB 3.0 and will introduce important IC Package design considerations and effective USB PCB design techniques. Topics include: How to Design for PCIe Gen 2/3 and performance requirements using HyperLynx 3D EM. (HyperLynx 3D EM product formerly known as IE3D™ EM)
This Webinar introduces important IC Package Design considerations, including an effective high-speed design methodology that has been successfully employed for the design of a commercial USB 3.0 package. USB 3.0 is rapidly being adopted by a growing number of system level companies, spawning many integrated device manufacturers (IDMs) to develop new chips to address this need. USB 3.0 supports data transfer rates up to 4.2 Gbits/sec, creating new challenges in the high-speed SERDES design process for the IC package designer and signal integrity engineer. These higher data rates will require substantially improved modeling accuracy of the IC Package Design interconnect, wire bonds, vias and solder balls. Full 3D electromagnetic (EM) simulation and modeling is required for such structures, to help ensure the package design is optimized for low cross-talk (EM coupling), reflection, and insertion loss.
What You Will Learn
- PCI Express (PCIe) Gen 2/3 performance requirements related to USB 3.0 and IC package design
- USB PCB design techniques to overcome design challenges
- How to correct typical mistakes and oversights made by inexperienced IC package designers
- How to use HyperLynx 3d EM to model packages.
About the Presenter
Manoj F. Nachnani is President and CEO of Enabling Solutions, Inc. The company is a leading provider of High Speed Package Designs, Package SI analysis, Power Delivery Analysis, and Characterization. Before starting Enabling Solutions, he was a manager at National Semiconductor for eight years, with the primary responsibility of providing high performance packaging solutions to the product designers. He also chaired the JEDEC JC15.2 committee for four years, which is responsible for developing characterization methodologies and standards. He has an MSEE and MS in Solid State Physics.
Who Should View
- IC Package Designers
- Signal Integrity Engineers
- Design Managers
- Engineering Managers
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