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Introduction of Electrical Signoff Process with HyperLynx



Signal integrity, power integrity, and EMI are big challenges for design teams. Even if signal and power integrity simulations are widely used, preparing the simulations (i.e. deciding which nets to simulate and gathering all the device models) requires a lot of effort. It can take hours to acquire results from EMI simulations, and it doesn’t tell you about the root cause.

This webinar discusses how to create a correct-by-design process, efficient simulation flow, and Electrical Signoff (ESO) process using Mentor Graphics’ HyperLynx tool suite.

What You Will Learn

  • How to manage system-level analysis more effectively
  • How to create correct-by-design process and Electrical Signoff process

About the Presenter

Presenter Image Minoru Ishikawa

Minoru Ishikawa joined Mentor Graphics eight years ago. Minoru is now a market development manager for HyperLynx DRC. He worked for Sony for sixteen years and he had been leading SI and EMC simulation at Sony since 1990. He has a Master degree in Electronics Engineering from Tohoku University in Japan.

Who Should View

  • PCB engineers
  • PCB designers
  • Engineering managers

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