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Manage PCB Trace Lengths for Optimal System Timing



Managing and constraining trace lengths on your PCB is vital to ensure that system timing is met. Determining those lengths requires an understanding of flight time, electrical length versus physical length, and loading on the net.

This webinar will discuss how to determine what those lengths need to be for PCB routing, and how to determine allowable trade-offs to meet system timing goals using signal integrity simulation. We'll also discuss the need to determine length matching based on electrical design goals through simulation, to allow more flexibility to meet layout constraints during PCB routing.

What You Will Learn

  • How to determine the best trace lengths for PCB routing
  • How to determine allowable trade-offs to meet system timing goals

About the Presenter

Presenter Image Patrick Carrier

Patrick Carrier worked as a Signal Integrity Engineer at Dell for 5 years before joining Mentor in September 2005. Patrick is now a technical marketing engineer specializing in analysis products, including signal and power integrity, EMC, and thermal design.

Who Should View

  • Board designers
  • Electrical engineers

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