Sign In
Forgot Password?
Sign In | | Create Account

Manage PCB Trace Lengths for Optimal System Timing

Details

Overview

Managing and constraining trace lengths on your PCB is vital to ensure that system timing is met. Determining those lengths requires an understanding of flight time, electrical length versus physical length, and loading on the net.

This webinar will discuss how to determine what those lengths need to be for PCB routing, and how to determine allowable trade-offs to meet system timing goals using signal integrity simulation. We'll also discuss the need to determine length matching based on electrical design goals through simulation, to allow more flexibility to meet layout constraints during PCB routing.

What You Will Learn

  • How to determine the best trace lengths for PCB routing
  • How to determine allowable trade-offs to meet system timing goals

About the Presenter

Presenter Image Patrick Carrier

Patrick Carrier worked as a Signal Integrity Engineer at Dell for 5 years before joining Mentor in September 2005. Patrick is now a technical marketing engineer specializing in analysis products, including signal and power integrity, EMC, and thermal design.

Who Should View

  • Board designers
  • Electrical engineers

Related Resources

Multimedia

Modeling Signal Discontinuities in SERDES Channels: Minding the Details without Breaking a Sweat

This webinar will go through the basic steps of creating 3D models for common PCB structures, and then using these models to analyze a high speed serial channel.…View On-demand Web Seminar

The Need for Speed and Accuracy: Techniques and Tools for Modern Signal-Integrity Analysis

This session will discuss the advanced techniques required for modern SI analysis, ranging from high-throughput batch simulation of memory interfaces to IBIS-AMI modeling of SERDES channels to 3D-electromagnetic...…View On-demand Web Seminar

Analyzing DDR2/3/4 Memory Interfaces: Guarantee Your Margins Before You Build and Ship Boards

This session will explain the use of HyperLynx’s DDRx Wizard, and preview its upcoming support for the new DDR4 standard.…View On-demand Web Seminar

Other Related Resources

High-Speed PCB Layout: Physical Design Issues of High-Speed Interfaces

White Paper: Moore’s law, applied to data rates, has pushed PCB circuits so fast that the layout becomes part of the circuit. In designs such as DDR3 and PCIe, the fastest memory and high-speed serial performance...…View White Paper

Advanced PCB Techniques: How To Use the Latest Technologies

White Paper: Every electronic product design has many challenges associated with the project. Often, the real challenge comes as an afterthought, perhaps the last line of the requirements document: “… and...…View White Paper

Understanding Via Effects

White Paper: As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs...…View White Paper

 
Online Chat