3D modeling methods in SERDES Designs: Is via behavior causing your SERDES designs to fail?
On-demand Web Seminar
Do you have a clear understanding of your Multi-Gbps channel’s performance? Are you accounting for the potential signal losses due to discontinuities, such as a poor via design? If not, the slightest misstep could cause your SERDES designs to fail.
Engineers take great care in designing vias for high-speed differential signals, especially for return-current and common-mode immunity. By using proper via-modeling methods early in the design process high-speed designers can configure correct via structures and accurately predict via noise effects.
In this webinar, we will evaluate the behavior of vias through 3D electromagnetic simulations and provide a methodology for optimizing via designs. We’ll also use post-route verification to validate via behavior for a better understanding of a via's effects on multi-gigabit channels.
What You Will Learn
- How to evaluate via behavior
- How to optimize via design
- The importance of 3D EM (electromagnetic) simulation
- Proper pre- and post-route via modeling techniques
About the Presenter
Dr. Zhen Mu
Dr. Zhen Mu is currently the product market manager at Mentor Graphics, responsible for signal integrity and power integrity products for printed circuit board and package analysis. Prior to Mentor, she worked at Cadence Design Systems as a member of the consulting staff and as the leading technologist for high-speed simulations. At Sycamore Networks, Dr. Mu was the principal signal integrity engineer for high-speed systems designs. Dr. Mu received her B.Sc. and M.Sc. degrees from the University of Science and Technology, Beijing China, in 1982 and 1985, respectively, and her Ph.D degree in Electrical and Computer Engineering from the University of Manitoba, Canada in 1994. Dr. Mu holds two US patents and one Canadian patent.
Who Should View
- SERDES designers
- Electrical engineers working with high-speed differential signals
- Digital designers
- Board designers
DDR4 and LPDDR4 - Board Design Verification and Challenges
In this on-demand presentation we dive into the differences between DDR4/LPDDR4 from their previous generation counterparts. Join us as we demonstrate the new features of HyperLynx 9.2.…
HyperLynx: Making Analysis More Accessible
This webinar discusses how to make analysis more accessible to everyone in your organization with HyperLynx and the VX release of Xpedition Enterprise.…
Other Related Resources
How to Use HyperLynx DRC to Identify SERDES Design Issues
White Paper: Many designs use SERDES interfaces to move data. Here, we’ll look at common layout requirements related to SERDES designs, and how HyperLynx DRC can help identify issues on PCB boards that violate...…
Computation of Time Domain Impedance Profile from S-Parameters: Challenges and Methods
White Paper: When computing time-domain impedance profile from measured S-parameters, we often face some problems caused by low quality of sampled S-parameters, such as insufficient resolution, band limiting, noise...…