3D modeling methods in SERDES Designs: Is via behavior causing your SERDES designs to fail?
On-demand Web Seminar
Do you have a clear understanding of your Multi-Gbps channel’s performance? Are you accounting for the potential signal losses due to discontinuities, such as a poor via design? If not, the slightest misstep could cause your SERDES designs to fail.
Engineers take great care in designing vias for high-speed differential signals, especially for return-current and common-mode immunity. By using proper via-modeling methods early in the design process high-speed designers can configure correct via structures and accurately predict via noise effects.
In this webinar, we will evaluate the behavior of vias through 3D electromagnetic simulations and provide a methodology for optimizing via designs. We’ll also use post-route verification to validate via behavior for a better understanding of a via's effects on multi-gigabit channels.
What You Will Learn
- How to evaluate via behavior
- How to optimize via design
- The importance of 3D EM (electromagnetic) simulation
- Proper pre- and post-route via modeling techniques
About the Presenter
Dr. Zhen Mu
Dr. Zhen Mu is currently the product market manager at Mentor Graphics, responsible for signal integrity and power integrity products for printed circuit board and package analysis. Prior to Mentor, she worked at Cadence Design Systems as a member of the consulting staff and as the leading technologist for high-speed simulations. At Sycamore Networks, Dr. Mu was the principal signal integrity engineer for high-speed systems designs. Dr. Mu received her B.Sc. and M.Sc. degrees from the University of Science and Technology, Beijing China, in 1982 and 1985, respectively, and her Ph.D degree in Electrical and Computer Engineering from the University of Manitoba, Canada in 1994. Dr. Mu holds two US patents and one Canadian patent.
Who Should View
- SERDES designers
- Electrical engineers working with high-speed differential signals
- Digital designers
- Board designers
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