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Simplify FPGA Design with VHDL-2008



VHDL has long been known as a verbose language and “strongly typed”. VHDL-2008 introduces various constructs with simplified syntax, and thus making it easier to use. While many may consider the changes and additions for VHDL-2008 good for only simulation; synthesis, too, reaps tremendous benefits from the new changes in the language standard. The amount of coding to get the same results has been reduced, the readability and reusability of the HDL has been increased, and complex structures are easier to implement without complex coding deployments.

Please join us in our brief webinar exploration of how VHDL-2008 can not only help simplify your HDL coding, but also help improve your overall design implementation.

What You Will Learn

  • Better HDL coding style
  • Efficient design optimization

About the Presenter

Presenter Image Bineet Srivastava

Bineet Srivastava has over 14 years of FPGA synthesis experience in the area of compiler development for HDLs (Verilog, SystemVerilog and VHDL). Prior to joining Mentor Bineet was with ST Microelectronics. He has done Computer Science from Kanpur University and Executive MBA from IIM Lucknow.

Who Should View

  • Design engineers
  • Engineering managers

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