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Xpedition Path Finder

Enables co-design across IC packaging and PCB domains to radically increase productivity

Technical Specifications

Xpedition Path Finder combines proven Xpedition Enterprise and other Mentor Graphics technologies into a powerful offering that enables BGA pin optimization, connectivity and constraint management, physical layout, electrical and thermal characterization and more.

Xpedition Path Finder Features

Generation of BGA pin-out optimized for routability

  • Design domain controlled optimization methodology
  • Rules-based, defined by user
  • Optimizes thru multiple levels of off-chip interfaces simultaneously
  • Supports multiple die, packages, and interposers

Connectivity management

  • Manages complete off-chip interconnect path through package and PCB
  • Supports multiple levels of off-chip interfaces
  • Integrated constraint management
  • Direct layout (OSAT) flow

Early design planning (feasibility studies)

  • Architected to work from partial data sets

Automatic library generation

  • Generation of optimized BGA symbols and footprints for PCB design

Complete IC-Package-PCB interconnect path optimization

  • Optimization of complete off-chip interconnect path in single pass

Physical design (Layout)

  • Logical and physical library data automatically generated.

Single layout tool for PCB, MCM, SiP, Hybrid and BGA designs

  • Reduces design times by orders of magnitude over competition.

Microsoft® based Component Object Model (COM) automation

  • COM is both a framework and an API that provides the ability to access, control, and manipulate data inside the tool.

Vertical stacking of parts

  • Interactive 3D stacking editor
  • Interposer support

Advanced die to die bonding

  • Die to die
  • Die to die to substrate
  • Reverse bonding

3D real-time DRC

  • Height control
  • Bond wire to die distance control

Concurrent team design

  • Patented technology enabling concurrent editing of schematic, constraints, and layout

Automatic break-out via pattern definition

  • Can be used on flip-chip bump array and package pins
  • Add blind, buried and through vias in user-defined patterns
  • Based on regions
  • Automatic escape routing for flip-chip
  • Controlled-angle fanouts

Plane generation support

  • True (WYSIWYG) plane data
  • Dynamic polygons
  • Trace plowing
  • Greater user control
  • Shape level overrides

I/O modeling

  • SPICE transistor level I/O model support
  • Direct support of IBIS behavioral level I/O models
  • Complete support for IBIS/AMI modeling

Power delivery modeling

  • Package and PCB level PDN modeling and analysis
  • Fully coupled SI and PI analysis
  • DC drop and AC power plane analysis
  • Coupled Thermal and PI analysis

DC drop analysis

  • Identify excessive voltage drop and high current densities
  • Determine if there is enough copper and stitching vias
  • Batch analysis of all power nets

AC power plane analysis

  • Optimize capacitor selection and mounting
  • Verify power supply impedance at IC power pins
  • Analyze voltage ripple on power nets

3D, full-wave EM analysis

  • 3D Method of Moments (MoM) engine
  • RF, microwave and HS digital signals

Quick and accurate S-Parameter generation

  • CFD based package thermal modeling/analysis
  • Design compare for partner collaboration.

Visual and report-based design data compare

  • Netlist and physical data comparisons (HTML & graphical outputs)
  • Semiconductor and OSAT collaboration

Industry-leading 3D wire profile editing

 
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