Nearly all PCB designs have some sorts of electrical performance flaws when first created. Finding and quantifying the severity of these design flaws remains a big challenge for design teams. Even if signal and power integrity simulation is widely used, preparing the simulations (i.e. deciding which nets to be simulated and gather all the device models) requires lots of effort. EMI simulations could take hours to acquire results, and they don’t tell you about the root cause.
This paper presents a better way to manage the Electrical Signoff (ESO) process to help achieve first time electrically-correct PCB designs. The ESO design practice described here is enabled using Mentor Graphics’ HyperLynx tool suite.