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FPGA I/O Optimization

Optimize FPGA I/O for PCB placement & routing

Technical Specifications

  • Supports the latest FPGA vendor devices
  • Bi-directional I/O optimization and pin-swapping based on actual PCB layout component orientation
  • Built-in I/O assignment rules specific to each device, simplifying pin assignments
  • Uses the generic FPGA symbol/symbol set from your corporate library, or allows you to create custom sets for a specific FPGA design
  • Identifies and documents which signal connections are made to device pins and how they map to original board-level bus structures
  • Manages data consistency between flows, automatically generating updated FPGA place and route constraints
  • Easy-to-use drag-and-drop graphical interface that updates on the fly
  • Imports LMS, EDIF and XML schematic symbols
  • Supported FPGA vendors: Actel, Altera, Lattice, Xilinx

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