HyperLynx Signal Integrity: Quick Tour
New users are attracted to HyperLynx by its intuitive user interface and extreme ease of use. As they become familiar with the tool, they quickly discover that it has the depth of technology to meet the Signal Integrity and Power Integrity Needs of the whole design team. The Quick Tour is aimed at design engineers who would like to see how HyperLynx efficiently supports routine signal integrity analysis tasks.
The tour is broken into chapters, each chapter focuses on a single signal integrity challenge. Each chapter starts with a brief description of the challenge, it is then followed by a detailed, step-by-step analysis of an example net. Signal integrity deficiencies in the design of the net are identified, corrections applied and validated.
Signal Integrity Quick Tour Contents
Section One: Pre-Layout Analysis
Designing a Well Behaved Simple Clock Net
Clock nets must be short of properly terminated to avoid excessive ringing. One consequence of ringing is “input ring-back”. This is when a signal fails to smoothly transition between the input threshold voltages of a receiver. It can result in false switching, meta-stable conditions and timing jitter. A schematic for a simple clock net is created and analyzed. The ring-back is quantified and parallel termination applied to eliminate.
Driver Strength and Overshoot Control
A second consequence of ringing is overshoot. This is when a signal swings past the supply or ground voltage. Excessive overshoot may saturate input transistors, slowing their switching time. In extreme cases it may even permanent damage ICs. A schematic for a second simple clock net is created using an IBIS driver model. The level of overshoot is measured using the typical, fast and slow driver characteristics. Series termination is applied to reduce overshoot.
The HyperLynx Termination Wizard
In the previous chapters a trial and error approach was used to choose termination values. In this chapter the HyperLynx Termination Wizard will be used to pick the optimal values for terminators.
Simulation with parameter sweeping allows you to study the effects of varying design property values. Passive and active component values can be swept, as can PCB geometric values. Sweeping can be used to optimize component values, do sensitivity analysis as well as solution space and reliability analysis. In this chapter a parameter sweeping will be applied to a series terminated net to determine the effect of changing driver strength and termination values.
HyperLynx supports two types of EMC analysis: spectrum analysis from current probes and prediction of the far field radiation at a specified point in space. Early detection of major EMC sources using current probes can avoid expensive redesign. In this chapter pre-layout EMC analysis will be demonstrated using a current probe on a net without adequate termination. The termination will be improved and the reduction in EMC.
Analyzing a more complex net: a simple DDR memory example
The examples used in previous chapters were simplified. In this chapter a net that is more typical of real world designs is analyzed. A DDR strobe net is simulated and waveform errors identified. The termination and trace lengths are then optimized to correct the waveform errors.
Designing a Multi-Gbps High Speed Serial Channel
High speed serial channels require more complex signal integrity analysis. In this chapter it will be demonstrated that in the HyperLynx world, more complex does not mean more difficult to use. The chapter starts with the skeleton of a multi-Gbps example net. SPICE driver and load models will be assigned as will accurate lossy coupled trace models. The net will then be analyzed using HyperLynx FastEye which offers accelerated statistical and linear channel analysis. The eye opening and BER bathtub curves will be developed for the net with and without transmitter de-emphasis.
Section Two: Post-Layout Analysis
Interactively Validating a Clock Net after Placement and Routing
Previous chapters have concentrated on pre-layout analysis. Fixing signal integrity problems early in the design process will provide enormous payback in the minimizing the cost of redesign and lost market opportunity. Even so, compromised are always present in the process of PCB layout and routing, so it is critical that post-layout signal integrity validation be conducted. In this chapter, interactive post-layout analysis will be used to identify a termination issue. The HyperLynx Termination wizard will be used to correct the problem.
Interactive Crosstalk Analysis
Nets on high density printed circuit boards will be subject to crosstalk from adjacent nets. In this chapter, an example net will be analyzed to establish which adjacent nets inject into it a significant crosstalk voltage. A crosstalk threshold voltage will be set in HyperLynx, so it can automatically extract the circuit for a net together with its neighboring nets to which it has strong coupling. The circuit will then be simulated to quantify the level of crosstalk.
Section Three: Additional Topics
PCB Layer Stack-up Editing and Trace Impedance Planning
Creating a good PCB layer stack-up is essential to meet the mechanical, signal and power integrity demands of a design. Trace impedance must be controlled to minimize reflections. Reliable return paths must be provided for signaling currents. Crosstalk must be limited. In addition, there must be adequate power distribution. In this chapter an example PCB layer stack-up will be created. Some of the critical elements of stack-up design will be discussed. Finally trace impedance planning will be done for single ended and differential nets.