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SERDES Design

Address common SERDES design challenges quickly and easily with HyperLynx SI

HyperLynx Signal Integrity delivers advanced tools for optimizing SERDES design projects. Its unique set of design and modeling capabilities maximize serial channel performance and reliability while avoiding common high-speed serial design problems, such as jitter, over/undershoot, ringing, crosstalk, losses, and reflections.

  • FastEye linear channel analysis
  • Statistical post processing of bit error rate information
  • IBIS-AMI characterization of pre-emphasis, equalization, and clock recovery

Key Features

SERDES design creation

HyperLynx SI provides the tools needed to create and validate designs incorporating the high speed serial channel standards that are now established in every segment of the electronics industry.

  • Supports all popular multi-Gbps SERDES design standards from consumer audio/video, computing, telecommunications and mobile phones
  • Provides a fast efficient virtual prototyping environment to conduct pre-layout high speed channel design tuning
  • Models advanced I/O architectures with pre-emphasis, equalization and complex clock recovery

Analysis and simulation

SERDES design analysis and simulation must combine model accuracy and simulation speed to enable designs to be tuned for maximum performance while providing adequate safety margins to accommodate component and manufacturing tolerances.

  • S-parameter simulation provides reliability, speed and accuracy in SERDES design. HyperLynx Simulate SI implements frequency-based simulation, with a complex pole-fitting algorithm, even with models that contain sparse frequency information.
  • Questa ADMS for efficient single kernel simulation. Simulate SI is the only SERDES design tool that provides efficient, simultaneous circuit- and system-level simulation, avoiding interprocess communication overhead incurred in alternate solutions.
  • FastEye analysis for extreme acceleration of channel simulation. HyperLynx SI FastEye suite uses linearized models for multi-Gbps drivers and receivers to simulate the propagation of more than a million bits per minute, validating 1e-15 BER performance in hours instead of days.
  • Pre- and post-layout analysis compatible with all major CAD vendor software. HyperLynx Simulate SI provides post-layout channel analysis to ensure layout compromises have not significantly impacted SERDES design performance.
 
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