Electronic System Level Design

Achieving Optimal Designs though Electronic System Level (ESL) Methodologies

Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. This trend toward increasing complexity has led to more ASIC re-spins, lost revenue from missed design deadlines, and sub-optimal systems that are larger, slower or consume more power than required.

Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies. Even more important, the single source methodology eliminates the most common source of errors between the system designer and the hardware designer. Designers can now use SystemC transaction-level modeling (TLM) to quickly perform architectural tradeoffs for power, performance and area, and evaluate hardware/software interactions. Designers can also use best-in-class high-level synthesis technology to support TLM-based processes, and automate the creation of optimized RTL implementations. Using this methodology, designers can create, optimize and verify designs that are tailored to their specifications 10-100X more efficiently than traditional methodologies.

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