Design-For-Test (DFT)

NEW: TestKompress Xpress

  • Methodology to ensure a design works correctly after manufacturing
  • DFT tools add test circuitry (RTL or gate level) for design testability
  • DFT tools generate test sets applied to manufactured designs to detect defects
  • DFT-based diagnostics facilitate failure analysis

Featured Design-For-Test Techpubs

Design Flows Using TestKompress

Different embedded compression products and technologies have been tried and discarded as the marketplace selects the solution that best meets all the requirements. Users have determined that a successful embedded compression tool is required to:

  1. Maintain high test quality (i.e. support all fault types)
  2. Achieve high test compression of both test time and test data (up to 100X)
  3. Have little or no impact on the functional design
  4. Add minimal area
  5. Easily fit into the design flow

As evidenced by its widespread industry adoption, TestKompress has met or exceeded all of these requirements while requiring as few as a single scan channel and offering diagnostics directly from compressed patterns. While Design-For-Test (DFT) groups are typically most concerned with high test quality and Operations Test is focused on reducing test time and data, design teams are most concerned with how any tool or methodology will impact the design and how it will fit into their existing design flow. This paper will describe the various design flows that TestKompress supports for the generation, insertion and synthesis of its embedded compression logic. The advantages of each flow are discussed so that the designer can decide which best fits into his or her existing design flow.

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At-Speed and Advanced Fault Models for Achieving High Quality Test

With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.

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Improving Yield - Bridging Fault ATPG in FastScan and TestKompress with Net Pair Identification using Calibre

This technical whitepaper discusses the necessary steps for generation of scan patterns that target particular net pairs within a design using the bridging fault model. In order to maximize the value of scan patterns, only net pairs that are likely to bridge because of their physical characteristics are targeted for this fault model. The process of using Calibre tools to identify a list of net pairs targeted for the bridging fault model will be discussed, as well as the steps needed for generating scan patterns to target the suspect net pairs using FastScan™ or TestKompress.

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