Top 10 Papers
Read about the latest, innovative techniques in Design-for-Test technology in subjects such as proven DFT solutions, high quality test, compression solutions and yield improvements. These articles and conference papers will give you insight on Mentor Graphics Design-for-Test technology.
Papers
Solutions
Proven DFT Solutions
Mentor's DFT products have been effectively used in billions of devices. Even products that are considered relatively new such as TestKompress are already used in over a billion devices and over one thousand designs. All Mentor DFT tools (including TestKompress and YieldAssist) are recommended in the latest TSMC and UMC reference flows.
- Renesas Technology Proves Success with Mentor Graphics TestKompress and a Customized Test Approach - Customer Success Story
- Reducing The Design Impact Of DFT In The Nanometer Era
Intel and Mentor Graphics- Electronic Design
Quality
Best Quality Test
Mentor Graphics provides the most effective test capabilities for all digital logic within a device. At-speed test using PLL with efficient false and multi-cycle path handling is critical for logic test. Memory BIST and MacroTest provide a complete solution to fully test memory devices with BIST or non-intrusively.
- Easily Implement PLL Clock Switching for At-Speed Test - Intel and Mentor Graphics, ChipDesign
- New Methods Test Small Memory Arrays - Test and Measurement World
- High-Frequency, At-Speed Scan Testing - IEEE Journal
Compression
Most Effective Compression
TestKompress provides the highest level of compression possible. This compression not only dramatically reduces test time (and data) but can also be used for dramatic reduction of test pins and signals. In fact, as few as 1 scan channel can be used within TestKompress blocks.
- Test Compression - Test & Measurement World
- X-Press Compactor for 1000x Reduction of Test Data - ITC 2006
- Embedded Compression for Production Test - Evaluation Engineering
Yield Improvement
Yield Improvement
YieldAssist is a new capability in failure diagnostics that ties scan test failures from testers to ranked physical problems and locations. It has direct links with the Calibre tools for viewing and works directly with TestKompress compressed patterns for volume on-line diagnostics.
- Scan Diagnostics in the Nanometer Design Era - Semiconductor Manufacturing, April 2006
- Yield Learning with Layout-aware Advanced Scan Diagnosis - CISCO, TSMC, Mentor Graphics
- Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning - ISTFA 2005<