BSDArchitect
- Automatically generates IEEE 1149.1 compliant boundary scan circuitry and boundary scan design language (BSDL)
- Supports Reduced Pin Count Testing (RPCT) for low cost test
- Creates verification test benches for quick and easy verification
- Provides BSDL compliance checking
- Supports technology-specific boundary scan cells and I/O pads
Benefits
- Saves weeks in boundary scan design generation
- Supports reduced-cost test
- Enables full chip test control
- Fits into any standard Verilog or VHDL design flow
Design-For-Test Resources
