IEEE Conference Papers

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SemiCon 2007

DFT Approaches Enable Mass Production Test
R Press, T Kobayashi, Mentor Graphics

ITC 2007

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
Chunsheng Liu, Yu Huang

Diagnose Compound Scan Chain and System Logic Defects
Y.Huang, WT Cheng, R.Guo, Mentor Graphics, W.Hsu, YS Chen, TSMC and A.Man, AMD 

Dynamic N-Detect Patterns Based on Equivalent Faults
P.Reuter, Y.Huang, Mentor Graphics

Enhanced Testing of Clock Faults
T.McLaurin, R.Slobodnik, ARM, KH Tsai, A.Keim, Mentor Graphics

Faster Defect Localization in Nanometer Technology based on Defective Cell Diagnosis
M.Sharma, WT Cheng, TP Tai, Mentor Graphics, YS Cheng, W.Hsu, TSMC, C.Liu and S.Reddy, University of Iowa, and A.Man, AMD

Interconnect Open Defect Diagnosis with Minimal Physical Information
C.Liu, S.Reddy, Univeristy of Iowa, W.Zou, WT Cheng, M.Sharma, H.Tang, Mentor Graphics

ATS 2007

Effect of IR-Drop on Path Delay Tsting Using Statistical Analysis
C.Liu, Y.Wu, University of Nebraska-Lincoln, and Y.Huang, Mentor Graphics

Fault Dictionary Based Scan Chain Failure Diagnosis
R.Guo, Y.Huang, WT Cheng, Mentor Graphics

Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead
C.Liu, S. Reddy, University of Iowa, H.Tang, WT Cheng, W.Zou, Mentor Graphics

Programmable Logic BIST for At-speed Test
Y.Huang, X.Lin, Mentor Graphics

Test Generation for Timing-Critical Transition Faults
X.Lin, M.Kassab, J.Rajski, Mentor Graphics

VTS 2007

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance
C Liu, Univ of Nebraska, Y Huang, Mentor Graphics