IEEE Conference Papers | 2005

ITC 2005 Conference Papers

Compressed Pattern Diagnosis For Scan Chain Failures
Y.Huang, W-T.Cheng, J.Rajski

Compression Mode Diagnosis Enables High Volume Volume Monitoring Diagnosis Flow
A.Leininger, P.Muhmenthaler, W-T Cheng, N.Tamarapalli, W.Yang, H.Tsai

Full-Speed Field-Programmable Memory BIST Architecture
X.Du, N.Mukherjee, W-T Cheng, S.Reddy

Chasing Subtle Embedded RAM Defects for Nanometer Technologies
T.Powell, A.Kumar, J.Rayhawk, N.Mukherjee

X-filter: Filtering unknowns from compacted test responses
M.Sharma, W-T Cheng

Built-In Constraint Resolution
G.Giles, J.Irby, D.Toneva, K.H.Tsai

ISTFA 2005

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning
C.Eddleman, N.Tamarapalli, W-T Cheng

ITSW 2005

Logic BIST Diagnostics Using Simple Synchronised MISR Unload
Chris Hill and Thomas Rinderknecht, Mentor Graphics

In this paper we present a conmercial logic BIST diagnostic approach; using an enhanced BIST controller that supports simple synchronised observation of the MISR on a per pattern basis, reinitialising the BIST controller. Selected patterns are unloaded and diagnostic inference identifies candidate faults and their locations. The approach is flexible and can be tailored to fit constraints of the test environment. At-speed BIST is supported, as is diagnostics through a low speed interface, such as IEEE 1149.1.