IEEE Conference Papers | 2006
ITC 2006 Conference Papers
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
H.Tang, S.Manish, J.Rajski, M.Keim, B.BenwareTest Smorgasbord: Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test
B. Suparjo, Mentor Graphics, A. Ley, ASSET InterTech, H. Ehrenberg, GOEPEL ElectronicsProduction Test Concerns: A Rapid Yield-Learning Flow Based on Production-Integrated Layoutaware Diagnosis
M. Keim, N. Tamarapalli, H. Tang, M. Sharma, J. Rajski, Mentor Graphics, C. Schuermyer, B. Benware, LSI LogicQuality Issues in Transition-Fault Testing: Improving Transition-Fault Test Pattern Quality Through At-Speed Diagnosis
N. Tendolkar, D. Belete, B. Schwarz, B. Podnar, S. Karako, Freescale Semiconductor, A. Gupta, The University of Texas at Austin, W. Cheng, A. Babin, K. Tsai, N. Tamarapalli, G. Aldrich, Mentor GraphicsAdvanced Diagnosis: Combined Electrical and Physical - Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology
V. Mehta, M. Marek-Sadowska, University of California, Santa Barbara; K-H. Tsai, J. Rajski, Mentor GraphicsData Compression Methodology and Modeling: X-Press Compactor for 1000x Reduction of Test Data
G. Mrugalski, J. Rajski, WT. Cheng, N. Mukherjee, Mentor Graphics; J. Tyszer, Poznan University of TechnologyCompression Diagnostics: Signature-based Diagnosis for Logic BIST
M. Sharma, W. Cheng, T. Rinderknecht, L. Lai, C. Hill, Mentor GraphicsDiagnosis Improvement: Diagnosis with Limited Failure Information
Y. Huang, W. Cheng, N. Tamarapalli, J. Rajski, R. Klingenberg, Mentor GraphicsTest Power Reduction: Preferred Fill: A Scalable Method to Reduce Capture Power for Scanbased Designs
X. Lin, J. Rajski, Mentor Graphics; S. Remersaro, S. Reddy, University of Iowa; I. Pomeranz, Purdue University