How to Simplify your Test Procedure File

Design-for-Test Technical News
June 2006

In some designs, it is necessary to initialize specific scan cells, such as PLL control or clock gating logic, to known values before generating patterns. Different procedures in the Test Procedure File can be used to apply known values to primary input pins in order to initialize the necessary registers but this can result in lengthy test_setup procedures that are hard to debug. Additionally, a new test procedure file will need to be loaded each time there is a change to the test_setup procedure in order to enable new clocks thus requiring the execution of all Design Rule Checks (DRCs).

Condition statements provide an easy way of specifying initialization values for scan cells within the design. For example, if a clock control register is normally initialized by the TAP controller to a known value in order to enable clock_1, the following condition statement may appear in the named capture procedure cycle instead of a test_setup procedure which requires manipulation of the TAP controller states:

procedure capture capture1 =
  timeplate tp1;
  condition /instance_control/clock_1_reg/reg_1/Q 1;
     cycle =
       force scan_en 0;
       force_pi;
       pulse clock_1;
    end;
    cycle =
        force_pi;
        measure_po;
        pulse clock_1;
    end;
end;

Since the ATPG tool will ensure that this register is correctly initialized during the capture cycle, there is no need to specify a sequence of values on primary input pins. This greatly reduces the complexity of the test procedure file. In cases where multiple test procedure files are used with different test_setup procedures to enable different clocks, you can instead use a condition statement in each named capture procedure, resulting in a single test procedure file and eliminating the need to execute Design Rule Checks (DRCs) multiple times.

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