Merging Clocks Within the Same Patterns
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The three main goals for ATPG tools are to:
Default ATPG uses only one clock pulsed at a time during the capture cycle. If multiple clocks are pulsed together then there is a risk that the skew between the clocks could result in a race condition. A sequential element using clk2 is expected to capture the values from clock pulses in the previous cycle. However, this clk2 element may unexpectedly capture a new value from an upstream device that updated early, which was clocked by clk1. Thus, the issue was a result of the old value not being held there long enough for clk2 to capture it. This is called a hold time problem. Today, the ATPG expert (create patterns –auto) recognizes when several clocks do not have interactions. As a result, they can be safely pulsed together. The manual command to pulse non-interactive clocks together is: Set clock restriction domain_clocks ATPG tools now use SDC files to define false and multicycle paths that are not intended to operate at system frequencies. We recently added hold time violation handling to our false and multicycle path handling for 2007_1 release. The ATPG tool uses this information to mask cells (X out) to avoid mismatches at the pattern validation phase. Now you can mask cells that are only interacting between clock domains while pulsing multiple clocks. With the added support of hold time violation a user can test cross domain interaction related to hold time violations. The new switch –hold is used as shown: The “cross_clock_domain” argument pulses all clocks. The “hold” argument X’s out any interaction between domains where the old and new values are not the same. There is a risk that two domains have many clocks. Consequently, it is a good practice to look at the domain interactions and avoid combining domains with lots of interactions.
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