Industry Articles

2008

High quality scan test with minimal pins Adobe Acrobat Document Jul 30

As IC Designs Get blah, blah, blah . . . Adobe Acrobat Document Jul 07

Test is a Four Letter Word Adobe Acrobat Document May 05

DFT, ATE drive yield improvement  Feb 05

DFM-oriented test ensures better yield Adobe Acrobat Document Jan 16

2007

Designers Must Yield to Change  Nov 01

The X Factor Adobe Acrobat Document Oct 15

Embedded Compression For Production Test Adobe Acrobat Document Oct 01

Rethinking DFT Strategies in Nanometer Designs Adobe Acrobat Document Sep 03

The Many Faces of Software Diagnosis Adobe Acrobat Document Aug 15

Launch-off-shift at-speed test Adobe Acrobat Document Jun 07

Leverage on-chip blocks for better at-speed tests Adobe Acrobat Document Jun 04

2006

Reducing The Design Impact Of DFT In The Nanometer Era Adobe Acrobat Document Oct 26

Using Timing Constraints For Generating At-Speed Test Patterns Adobe Acrobat Document Oct 04

Test Compression - does compression need to be 100 times better Adobe Acrobat Document Oct 01

Choosing an IC Test Plan Adobe Acrobat Document Sep 08

Scan Diagnostics in the Nanometer Design Era Adobe Acrobat Document Apr 22

Easily Implement PLL Clock Switching for At-Speed Test  Apr 10

Taking Advantage of Scan for Yield Improvement  Feb 24

2005

Meeting yield enhancement challenges  Dec 01

Test diagnostic tool helps to increase yields Adobe Acrobat Document Oct 31

Test Takes New Role in Yield Improvement Adobe Acrobat Document Oct 17

Scan-Based Diagnostics Adobe Acrobat Document Oct 06

Test Pattern Compression Saves Time and Bits Adobe Acrobat Document Jul 13

Evaluating test compression options  Jul 12

Adopting the Right Embedded Compression Solution Adobe Acrobat Document May 03

High Octane ATPG Adobe Acrobat Document May 01

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"  Feb 07

2004

DFM: You Can't Fix What You Don't Know Adobe Acrobat Document Dec 03

TestKompress: Why it is the Industry Standard for Compression Adobe Acrobat Document Dec 03

PLL Based At-Speed Testing Adobe Acrobat Document Dec 03

TestKompress in a Magma Blast Flow Adobe Acrobat Document Dec 03

DFT Techniques for Structural Control of Multi-Cycle Paths Adobe Acrobat Document Dec 03

Embedded Memory Test Patterns at 130nm and Below Adobe Acrobat Document Dec 03

Revving up Memory Test: New At-Speed Techniques Adobe Acrobat Document Dec 03

Total Test Quality and the Quest for Zero DPM Adobe Acrobat Document Dec 03

Hierarchical DFT Methodology: A Case Study Adobe Acrobat Document Dec 02

Realizing High Test Quality Goals with Smart Test Resource Usage Adobe Acrobat Document Dec 02

ATE Data Collection -- A Comprehensive Requirements Proposal to Maximize ROI of Test Adobe Acrobat Document Dec 02

2003

Novel DFT schemes get real results  Oct 13

DFT Circuit Designers Battle IC, PC-Board Complexities  Jun 16

New methods test small memory arrays Adobe Acrobat Document Feb 03

2002

Yes, You Can Get A Testable SoC Design To Market On Time  Nov 25

On-time Finish Rests With Multiple Clocks  Apr 15

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