Industry Articles
2008
High quality scan test with minimal pins
As IC Designs Get blah, blah, blah . . .
2007
Designers Must Yield to Change
Embedded Compression For Production Test
Rethinking DFT Strategies in Nanometer Designs
The Many Faces of Software Diagnosis
2006
Reducing The Design Impact Of DFT In The Nanometer Era
Using Timing Constraints For Generating At-Speed Test Patterns
Test Compression - does compression need to be 100 times better
Scan Diagnostics in the Nanometer Design Era
2005
Meeting yield enhancement challenges
Test diagnostic tool helps to increase yields
Test Takes New Role in Yield Improvement
Test Pattern Compression Saves Time and Bits
Evaluating test compression options
Adopting the Right Embedded Compression Solution
Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"
2004
Test experts ponder cost of defects
Defects driving IC test strategies
ITC keynoters say designers need IC yield data
ITC Speakers Address Yield Enhancement
Magma and Mentor Graphics Announce TestKompress Integration into RTL-to-GDSII Flow (issued by Magma)
Mentor, Magma Create RTL-to-GDSII Flow
Magma and Mentor Graphics Announce TestKompress Integration into RTL-to-GDSII Flow
BIST tool tackles embedded memories
Mentor, Artisan Cooperate on Memory BIST
Mentor Graphics Announces Automated Functionality in FastScan and TestKompress DFT Tools
Mentor automates test tools, adds guru to staff
Smart test for nanometer designs
Improving Manufacturing Test Quality; Multiple Detection for Higher... (German Publication)
Putting Memory to the Test in Nanometer Designs
Enhancing Manufacturing Test and Yield in the Nanometer Era
2003
Leading-Edge Diagnostic Tools Help Ramp Up SoC Production
Traveling at the speed of memory
Novel DFT schemes get real results
High-Frequency, At-Speed Scan Testing, Design & Test of Computers
DFT Circuit Designers Battle IC, PC-Board Complexities
Interview with Mentor Graphics
