Industry Articles

2008

• DFT, ATE drive yield improvement  Feb 05

2007

• Designers Must Yield to Change  Nov 01
• The X Factor  Oct 15
• Embedded Compression For Production Test  Oct 01
• Rethinking DFT Strategies in Nanometer Designs  Sep 03
• The Many Faces of Software Diagnosis  Aug 15
• Launch-off-shift at-speed test  Jun 07
• Leverage on-chip blocks for better at-speed tests  Jun 04

2006

• Reducing The Design Impact Of DFT In The Nanometer Era  Oct 26
• Using Timing Constraints For Generating At-Speed Test Patterns  Oct 04
• Test Compression - does compression need to be 100 times better  Oct 01
• Choosing an IC Test Plan  Sep 08
• Scan Diagnostics in the Nanometer Design Era  Apr 22
• Easily Implement PLL Clock Switching for At-Speed Test  Apr 10
• Taking Advantage of Scan for Yield Improvement  Feb 24

2005

• Meeting yield enhancement challenges  Dec 01
• Test diagnostic tool helps to increase yields  Oct 31
• Test Takes New Role in Yield Improvement  Oct 17
• Scan-Based Diagnostics  Oct 06
• Physical Connection  Sep 15
• Test Pattern Compression Saves Time and Bits  Jul 13
• Evaluating test compression options  Jul 12
• Adopting the Right Embedded Compression Solution  May 03
• High Octane ATPG  May 01
• Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"   Feb 07

2004

• Test experts ponder cost of defects  Nov 08
• Defects driving IC test strategies  Oct 28
• ITC keynoters say designers need IC yield data   Oct 27
• ITC Speakers Address Yield Enhancement  Oct 27
• Magma and Mentor Graphics Announce TestKompress Integration into RTL-to-GDSII Flow (issued by Magma)  Oct 25
• Mentor, Magma Create RTL-to-GDSII Flow   Oct 25
• Magma and Mentor Graphics Announce TestKompress Integration into RTL-to-GDSII Flow  Oct 25
• BIST tool tackles embedded memories  Oct 08
• Mentor, Artisan Cooperate on Memory BIST  Oct 07
• Mentor Graphics and Artisan Develop High Quality Embedded Memory Testing with Advanced BIST Architecture  Oct 06
• Mentor Graphics Announces Automated Functionality in FastScan and TestKompress DFT Tools  Oct 05
• Mentor automates test tools, adds guru to staff  Oct 05
• Good Bridge Testing Needed  Oct 04
• Smart test for nanometer designs  Oct 01
• Improving Manufacturing Test Quality; Multiple Detection for Higher... (German Publication)  Oct 01
• Putting Memory to the Test in Nanometer Designs  Oct 01
• At-speed Testing Made Easy  Sep 13
• Enhancing Manufacturing Test and Yield in the Nanometer Era  Sep 13
• At-speed Testing Made Easy  Jun 04
• Enhancing manufacturing test and yield in the 90nm era  Jun 01
• Predicting Yield using Test-Based Fault Localization  Apr 01

2003

• Leading-Edge Diagnostic Tools Help Ramp Up SoC Production  Nov 10
• Traveling at the speed of memory  Oct 24
• Novel DFT schemes get real results  Oct 13
• High-Frequency, At-Speed Scan Testing, Design & Test of Computers  Sep 02
• DFT Circuit Designers Battle IC, PC-Board Complexities  Jun 16
• Interview with Mentor Graphics  Jun 01
• Improving Test Quality and Reducing Escapes  Apr 01
• New methods test small memory arrays  Feb 03

2002

• Yes, You Can Get A Testable SoC Design To Market On Time  Nov 25
• On-time Finish Rests With Multiple Clocks  Apr 15
• DFT Techniques for Total Test Quality  Jan 28