DFT, Design-For-Test Technical Publications, White Paper, Tech Paper, Technical Paper

Embedded Deterministic Test - DFT Technology for High-Quality Low-Cost IC Manufacturing Test

As the semiconductor technology migrates to 0.13 micron and below, it is becoming increasingly clear that test sets for single stuck-at faults alone are not sufficient to achieve the required quality levels. At 0.13 micron and below, circuits are more susceptible to speed related defects and hence to attain good quality, at-speed test sets such as those based on transition and path delay faults are necessary. While these additional test sets improve the test and product quality, they further exacerbate the problem of rising test data volume and test application time.

Design Flows Using TestKompress

Different embedded compression products and technologies have been tried and discarded as the marketplace selects the solution that best meets all the requirements. Users have determined that a successful embedded compression tool is required to:

Maintain high test quality (i.e. support all fault types)
Achieve high test compression of both test time and test data (up to 100X)
Have little or no impact on the functional design
Add minimal area
Easily fit into the design flow

As evidenced by its widespread industry adoption, TestKompress has met or exceeded all of these requirements while requiring as few as a single scan channel and offering diagnostics directly from compressed patterns. While Design-For-Test (DFT) groups are typically most concerned with high test quality and Operations Test is focused on reducing test time and data, design teams are most concerned with how any tool or methodology will impact the design and how it will fit into their existing design flow. This paper will describe the various design flows that TestKompress supports for the generation, insertion and synthesis of its embedded compression logic. The advantages of each flow are discussed so that the designer can decide which best fits into his or her existing design flow.

At-Speed and Advanced Fault Models for Achieving High Quality Test

With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.

Improving Yield - Bridging Fault ATPG in FastScan and TestKompress with Net Pair Identification using Calibre

This technical whitepaper discusses the necessary steps for generation of scan patterns that target particular net pairs within a design using the bridging fault model. In order to maximize the value of scan patterns, only net pairs that are likely to bridge because of their physical characteristics are targeted for this fault model. The process of using Calibre tools to identify a list of net pairs targeted for the bridging fault model will be discussed, as well as the steps needed for generating scan patterns to target the suspect net pairs using FastScan or TestKompress.

The Robustness of Various Test Compression Techniques

Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TestKompress has now been used in roughly one billion production chips. There has been a surge of compression techniques promoted in the industry since TestKompress was released in 2003. So, why has TestKompress become the standard approach in industry? This paper will try to explain the technology behind the various compression techniques and their robustness in the presence of Xs, false and multi cycle paths, low pin access, and other design factors.

TestKompress 2007

To help increase product test quality while improving time-to-market and performance, the market leading automated test pattern generation (ATPG) tools have been significantly enhanced for 2007. This paper describes an overview of major enhancements that were made to the ATPG tools FastScan and TestKompress.

The Next Generation of Embedded Test Compression: TestKompress(r) Xpress Compactor

The new embedded compression hardware used by TestKompress called Xpress provides significant improvement in compression of test data and test application time for designs with large number of Xs. This paper provides an overview of test quality and cost requirements of nanometer designs as well as the impact of X sources on test quality. A high-level description of the Xpress hardware is followed by benchmark results from industrial designs of Mentor's customer partners.

High Quality Test Solutions for Secure Applications

Designs for secure applications such as smart cards and those used in the defense industry require security to ensure sensitive data is inaccessible to outside agents. Conversely, scan chains have been used for decades to improve access to internal logic for automatic tester equipment (ATE) so that devices can be tested efficiently and quickly. This conflict in requirements has forced many designers of secure applications to use logic BIST and sacrifice test quality in some cases, or perform deterministic scan test in very costly secure test environments. Contributing to these challenges are the ever-increasing requirements for high quality test and additional test requirements for fabrication processes at smaller geometries. In this paper, we will explore the techniques currently in use for testing devices designed for secure application and review the benefits and challenges of each available solution.

Solving the Challenges of Testing Small Embedded Cores and Memories Using FastScan MacroTest

FastScan MacroTest is a breakthrough technology that automates the generation of manufacturing test vectors for small, embedded cores and memories while minimizing the impact on performance, reducing the area of the design, and increasing overall product quality.

Testing Large-Capacity CAM with MBISTArchitect and FastScan MacroTest

Testing Large-Capacity CAM with MBISTArchitect and FastScan MacroTest. Classical memory testing techniques typically do not address the unique testing requirements of content addressable memory (CAM). This whitepaper describes a flow for testing CAM models using a combination of MBISTArchitect and FastScan MacroTest.

At-Speed Embedded Memory Test

At-speed testing is growing in importance as designs move to process technologies of 130nm and below. This publication focuses on various aspects of at-speed testing of embedded memories, including how at-speed testing improves test quality, what are the best at-speed memory test techniques, and how to implement an effective at-speed memory test strategy.

Achieving High-Quality Test for ARM Artisan Memories

High quality testing of today's nanometer designs is increasingly more essential - and more complicated. One aspect of this, memory testing, is becoming more of a concern as well. Not only is the amount of memory increasing, but the diversity of memories in an SoC design is also growing. Embedded memory has a wide range of uses, speeds, sizes, and configurations. Because memories are such dense structures, they are more susceptible to defects than logic. Understanding and detecting these defects is the key to developing a good memory test plan. Memory IP suppliers, such as ARM®, recommend a set of algorithms for testing their memories based on architecture and implementation. The partnership between Mentor Graphics® and ARM enables joint customers to easily develop high quality test for memories, which is a foundational part of any test strategy. This paper discusses both the memory testing algorithms recommended by ARM and how MBISTArchitect can be used for thorough testing, diagnosis and repair of these memories.

Beyond Pass/Fail Testing: Using Failure Data from Manufacturing Test for Yield Monitoring and Learning

As feature sizes shrink, the number of non-visual defects increases. At the same time, traditional methods for defect identification and yield learning are becoming less effective. Scan design has been the enabling technology for high quality manufacturing test for many years. Now with advanced diagnostics capabilities, a company's investment in scan design can now be used for yield learning and yield monitoring. If properly leveraged, scan-based test and diagnostics can play an important role in yield learning and yield monitoring for nanometer design.

YieldAssist and Its Successful Industrial Applications

Yield Improvement, Verified Flow, Accuracy, Layout Aware and Volume DiagnosisFeature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnostics targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The sorted, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. YieldAssist, Mentor's scan diagnosis solution has been adopted by many customers to meet these goals. This paper explains the technology behind it, discusses its applications and shows the results.

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