DFT Technical Publications

The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying RPCT, devices can be easily tested on structural DFT testers at a cost of about $200/pin compared to the high-end functional testers that cost almost $8,000-10,000/pin.

By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. We were able to free up device I/O by 90%. The method proposed here enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.

Different embedded compression products and technologies have been tried and discarded as the marketplace selects the solution that best meets all the requirements. Users have determined that a successful embedded compression tool is required to:

1. Maintain high test quality (i.e. support all fault types)
2. Achieve high test compression of both test time and test data (up to 100X)
3. Have little or no impact on the functional design
4. Add minimal area
5. Easily fit into the design flow

As evidenced by its widespread industry adoption, TestKompress has met or exceeded all of these requirements while requiring as few as a single scan channel and offering diagnostics directly from compressed patterns. While Design-For-Test (DFT) groups are typically most concerned with high test quality and Operations Test is focused on reducing test time and data, design teams are most concerned with how any tool or methodology will impact the design and how it will fit into their existing design flow. This paper will describe the various design flows that TestKompress supports for the generation, insertion and synthesis of its embedded compression logic. The advantages of each flow are discussed so that the designer can decide which best fits into his or her existing design flow.

 This application note describes the steps for viewing potential defect sites in the physical environment by directly reading the FastScan/TestKompress diagnostics output into Calibre and highlighting each location in the layout using Calibre DESIGNrev.