Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test
Contributor: Ron Press
Format: PDF Document
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying RPCT, devices can be easily tested on structural DFT testers at a cost of about $200/pin compared to the high-end functional testers that cost almost $8,000-10,000/pin.
By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. We were able to free up device I/O by 90%. The method proposed here enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.