DFT Technical Publications

High quality testing of today's nanometer designs is increasingly more essential - and more complicated. One aspect of this, memory testing, is becoming more of a concern as well. Not only is the amount of memory increasing, but the diversity of memories in an SoC design is also growing. Embedded memory has a wide range of uses, speeds, sizes, and configurations. Because memories are such dense structures, they are more susceptible to defects than logic. Understanding and detecting these defects is the key to developing a good memory test plan. Memory IP suppliers, such as ARM®, recommend a set of algorithms for testing their memories based on architecture and implementation. The partnership between Mentor Graphics® and ARM enables joint customers to easily develop high quality test for memories, which is a foundational part of any test strategy. This paper discusses both the memory testing algorithms recommended by ARM and how MBISTArchitect™ can be used for thorough testing, diagnosis and repair of these memories.

At-speed testing is growing in importance as designs move to process technologies of 130nm and below. This publication focuses on various aspects of at-speed testing of embedded memories, including how at-speed testing improves test quality, what are the best at-speed memory test techniques, and how to implement an effective at-speed memory test strategy.