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Electrical & Wire Harness Design Blog

Posts tagged with 'Open Verification Methodology'

22 Feb, 2011

J VanDomelen The hot news in mil/aero this week centers on UVM, Universal Verification Methodology (UVM) released yesterday by Accellera. The electronics industry organization, which is focused on electronic design automation (EDA) and intellectual property (IP) standards, has approved version 1.0 of its UVM standard for verifying integrated circuit (IC) designs. Accellera’s Verification IP (VIP) Technical … Read More

UVM, Universal Verification Methodology, Milaero, Open Verification Methodology, OVM, TSC, Accellera, Mentor, IC, Mentor Graphics, integrated circuit, Mentor.com, Mil-Aero, electronic design automation, IP, intellectual property, John Lenyo, Verification IP (VIP) Technical Subcommittee (TSC), VIP

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