Electronic System Level Design
Achieving Optimal Designs through ESL Methodologies
Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies and offers much shorter and efficient design cycles.
Full-Chip High-Level Synthesis
Catapult C Synthesis now delivers the first unified solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single ANSI C++ source. Combined with its new low-power optimizations, Catapult takes high-level synthesis to a new level and opens the way to true full-chip synthesis. Learn more about Catapult C Synthesis
Mentor Graphics Low-Power Design Press Conference, DAC 2009
Technology Overview:
The Vista platform offers comprehensive architecture design and prototyping allows users to model, analyze and optimize power at the transaction level of abstraction. View Technology Overview
ESL Design Tasks
ESL Design and Verification
Uses design creation and verification process at a higher level of abstraction to architect and validate system and SoC designs. It ensures that an optimal system that meets functionality, performance and power is built correctly first time. Learn More
- On-demand Web Seminar: Making the Right Architectural Decisions
High Level Synthesis
As design complexity pushes traditional RTL design and verification to their limits, High Level Synthesis reduces the manual effort required to create and verify synthesizable RTL code. Learn More
- Product Demo: Catapult C Synthesis - Overview
ESL Design Resources
Transaction Level Modeling
Transaction level modeling (TLM) provides an abstract design methodology supporting modeling, validation analysis and implementation processes. TLM is one of the key ESL concepts that allows modeling communication at a higher level while abstracting hardware signals, cycles and data structures. More
Partners and Standards
Partnering with a variety of different silicon vendor and flow partners allows Catapult C Synthesis to be used by ASIC and FPGA hardware designers in today’s leading wireless, video, and image processing applications. More
Catapult Industry Solutions
Catapult C broadband wireless, video, image processing solutions. More
Training
The courses have been tailored for audiences with varying backgrounds - from algorithm research and implementation teams to production quality hardware design teams.
- Catapult C
- C++ for Hardware Design
- C++ Coding Guidelines for Catapult C
From the Blogs
Take the High Road to Power-Optimized RTL
The latest edition of Chip Design Magazine features an insightful head-to-head discussion between Atrenta’s Kiran Vittal and Mentor’s Shawn McCloud. The topic: how to best achieve power-optimized RTL. Should…View Blog Post
News & Press
- Mentor Graphics Catapult C Adds SystemC Synthesis and Expands Full-Chip Capabilities
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu QNET to Achieve Significant Reduction in Power Consumption
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions Limited for Design and Consulting Services
- More