Electronic System Level Design

Achieving Optimal Designs through ESL Methodologies

Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies and offers much shorter and efficient design cycles.

Full-Chip High-Level Synthesis

Catapult C Synthesis now delivers the first unified solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single ANSI C++ source. Combined with its new low-power optimizations, Catapult takes high-level synthesis to a new level and opens the way to true full-chip synthesis. Learn more about Catapult C Synthesis

High Level Synthesis On-Demand Web Seminar

Learn how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. View Presentation

Download Algorithmic C Data Types Libraries

The Algorithmic CTM arbitrary-length bit-accurate integer and fixed-point data types allow designers to easily model bit-accurate behavior in their designs. Download the free libraries

Evaluate Catapult C Synthesis

Catapult C Synthesis is a High Level Synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment. Request Evaluation Software

Evaluate Vista Design

Vista is the industry's most advanced SystemC debug toolset, providing powerful HW and C/C++ oriented views and debugging mechanisms. Vista can naturally link into any SystemC environment and kernels. Evaluate Today

Catapult Product Demo

This demo will take you through the evolution of High-Level Synthesis, philosophy and future of Catapult and a demonstration of Catapult Synthesis. View Product Demo

ESL Design Tasks

ESL Design and Verification

Mentor provides ESL tools and methodologies that can be deployed to architect and validate hardware and software, ensuring an optimal system is built correctly the first time. Learn More

High Level Synthesis

As design complexity pushes traditional RTL design and verification to their limits, High Level Synthesis reduces the manual effort required to create and verify synthesizable RTL code. Learn More

ESL Design Resources

Transaction Level Modeling

Transaction level modeling (TLM) provides an abstract design methodology supporting modeling, validation analysis and implementation processes. TLM is one of the key ESL concepts that allows modeling communication at a higher level while abstracting hardware signals, cycles and data structures. More

Partners and Standards

Partnering with a variety of different silicon vendor and flow partners allows Catapult C Synthesis to be used by ASIC and FPGA hardware designers in today’s leading wireless, video, and image processing applications. More

Catapult Industry Solutions

Catapult C broadband wireless, video, image processing solutions. More

Training

The courses have been tailored for audiences with varying backgrounds - from algorithm research and implementation teams to production quality hardware design teams.

  • Catapult C
  • C++ for Hardware Design
  • C++ Coding Guidelines for Catapult C

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