Catapult C Synthesis - Adds Control-Logic and Low-Power Synthesis
Catapult C Synthesis announces technology which combines algorithmic and control-logic synthesis while dramatically reducing power consumption with new built-in low-power optimizations. Enables full-chip synthesis from ANSI C++.
New Features
New Features
Control-Logic and Low-Power Announcement Highlights
Catapult C Synthesis unveiled breakthrough enhancements for control-logic synthesis and low-power design.
This short video provides an overview of the announcement and reviews the key features and benefits taking HLS to the next level.
Control-Logic and Low-Power Announcement HighlightsTechnology Overview
Multi-level Clock Gating
Multi-level Clock Gating
Multi-Level Clock Gating with Catapult C Synthesis
With its new multi-level clock gating optimization, Catapult C automates a major low-power design technique and delivers unrivalled power reduction.
This video explains how Catapult C’s low-power analysis and optimizations can help designers reduce power by up to 90%.
Multi-Level Clock Gating with Catapult C SynthesisTechnology Overview
Control-Logic Synthesis
Control-Logic Synthesis
Abstraction and Benefits with Control-Logic Synthesis
Algorithmic synthesis delivers routinely proven benefits. But can control-logic provide comparable results?
This short video reviews the opportunities to improve productivity using the new Catapult C control-logic capabilities
Abstraction and Benefits with Control-Logic SynthesisTechnology Overview
Verification
Verification
The Catapult C Verification Edge
When and how the interactions between control-logic blocks and algorithmic units should be verified?
This video presents Catapult C SCReplay, a genuinely novel and patent-pending verification solution which addresses this fundamental question.
The Catapult C Verification EdgeTechnology Overview
Full-Chip High-Level Synthesis
Catapult C Synthesis now delivers the first unified solution that lets designers model, verify, and synthesize complex mixes of control and algorithmic units from a single ANSI C++ source. Combined with its new low-power optimizations, Catapult takes high-level synthesis to a new level and opens the way to true full-chip synthesis.
Catapult C Synthesis offers a quick and easy path from abstract C specifications to high-quality hardware implementations.
Catapult C Synthesis is the industry's choice for high-level synthesis.
- Fastest time to verified RTL
- ROI and time savings from the first design
- Easy to deploy within design organizations
New in Catapult C Synthesis
- Support for control-logic synthesis from pure C++
- Decoupling Control Channel (DCC) technology allows easy interfacing between algorithmic blocks and control-logic blocks
- Accuracy for control units where you need it
- Abstraction for algorithmic blocks meaning faster verification, better results
- New patent-pending SCReplay for visibility and debug during verification
- Fully automated multi-level clock-gating providing near perfect clock gating
- Dynamic power management interfaces
- Reduces power consumption by an average 40%
Product Demos
Overview
Catapult C Synthesis - Overview
Product DemoSee how to create, synthesize, and verify several RTL implementations from the same C++ source using Catapult C Synthesis. View Video
Control
Catapult C Synthesis - Control Logic Demo
Product DemoSee how Catapult enables the design and synthesis of mixed control and algorithm block system-level designs written in C++. View Video
Low Power
Catapult C Synthesis - Advanced Clock Gating Demo
Product DemoSee how clock-gating optimizations are applied to a design by Catapult, and how the physical power savings are measured using integrated dynamic power analysis flows. View Video
Resources
Advanced Clock Gating Techniques in Catapult C Synthesis
Techpub: This whitepaper discusses one of the most important power optimization techniques used in Catapult C Synthesis – advanced clock gating optimization and analysis. Electronic System Level (ESL) design... View Techpub
Designing Better Broadband Wireless Algorithms for ASIC
On-demand Web Seminar:
In this webinar, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. View On-demand Web Seminar
Learn More
Thomas Bollaert’s Blog
- 46th DAC / STMicroelectronics designs a Frequency Domain Processor out of pure C++
- 46th DAC / Hitachi reports 8 tape-outs with Catapult C
- Catapult C Synthesis, the 46th DAC “Must-see” product according to analysts
- Synthesizing parallel designs from sequential C++ - part 2
- Synthesizing parallel designs from sequential C++ - part 1
User Reviews
What Others Are Saying
“The new Catapult extensions for control-logic synthesis now allow us to model, synthesize and verify our complete system from a single C++ source. By doing so, we avoid traditional integration problems and considerably reduce our design and verification effort. This represents a decisive breakthrough which we plan to capitalize on.”
Professor Schlicht, Head of Department, Fraunhofer
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