Platform Design and Verification Solution

Consumer, mobile, networking and storage systems with multi-core SoCs are rapidly becoming more complex, making architecture decisions increasingly critical and directly impacting competitive advantage. Configuring and verifying multi-core hardware/software architectures, and ensuring the system can carry its load and data traffic capacities, are all critical tasks.

Architecture Design

TLM 2.0-based Solution
Vista™ Architect is a complete TLM 2.0-based solution for architecture exploration and verification enabling system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems, understand the key scaling algorithms, and ensure optimized architecture, shorter implementation cycle and first time success.

Top-Down TLM Modeling
Vista Architect offers top-down TLM modeling (Vista Model Builder) tool, a set of key architecture models that can be easily configured, an intuitive graphical assembly platform (Visual SD), and advanced HW/SW debug and analysis toolset. The models can be intuitively set for various architecture configurations, interconnect layering and memory hierarchies.

Quickly Change the Micro-Architecture
The unique layered timing approach offered by Vista Architect enables users to quickly change the micro-architecture of each model defined by the Timing Policies and test various configurations while keeping functionality intact. Users can scale and tune timing and power accuracy from high-level approximation down to the target bus and protocol in a matter of minutes. Complex data packets can be easily created and tag with an “ID” and traced and analyzed as they propagated in the system. This unique capability allow users to better understand data flow and loading scenarios. Users can exercise statistical and randomized data traffic simulation or run SW-driven simulation with a target processor, testing realistic use cases and functionality.

Powerful Analysis Toolset
Vista Architect has a powerful analysis toolset that allows a user to intuitively view and analyze different performance and power metrics, look at load peaks, average latencies, throughput and utilization on any port, bus or sub-system.

Rapidly Prototype Systems
With Vista Architect users can rapidly prototype systems with the key hardware blocks and analyze power and performance under different scenarios and traffic loads. The scalable modeling approach supported in Vista enables design teams to manage timing and power budgets from concept down to the desired implementation, ensuring silicon is optimized, can carry the data capacities for a given application and is scalable to support future derivation of the product.