High Level Synthesis Workshop: Crossing the Gap between Algorithm and Hardware Implementation

Select aHands-on Workshop

Overview

Come to a one-day workshop to learn how C++ and Catapult Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms.

In this workshop you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. We will show you through a series of presentation material and lab exercises how untimed "pure" C++ algorithms can be turned into high-performance RTL implementations. You will see how the area, latency, and throughput of an algorithm can be optimized, and RTL code created, in minutes instead of the days or weeks required for VHDL or Verilog coding. You will experience our integrated verification environment to automatically validate the generated RTL functionality against the original C++ design without any need for the RTL design engineer to create an HDL testbench, or deal with vector capture and synchronization.

Powerful system level concepts for streaming data between concurrent hierarchical blocks will be covered to illustrate how high performance hierarchical systems can easily be created with C++ and tuned to meet aggressive throughput requirements.

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.

This all day hands-on workshop starts at 9:00am and ends at approximately 4:00pm