ESL Symposium Panel Discussion at DAC 2007

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Overview

The Missing Link: In Search of an ESL-to-RTL Design Flow

Electronic system level (ESL) design methodologies raise design activities to a higher level of abstraction, enabling more freedom for architecture exploration, early system design feedback, faster and more reliable system IP design and integration, early HW/SW development, increased productivity, and reduction in pre-silicon bugs. However, designers continue to debate an important point: How much does ESL design need to link with traditional RTL methodologies in order to fully realize its potential and deliver the promised return on investment.

Looking to the past, the electronics industry went through a similar process during the transition from gate-level to RTL design. Early niche applications of RTL eventually grew to become the mature, complete RTL-to-Gates methodology we know today. Now the industry faces a similar challenge in building an ESL-to-RTL flow.

What do we need to do to develop an industry standard flow and methodology? How do the ESL and RTL domains connect today? What elements are missing? Of the missing elements, which need to be addressed first? Plus, how can ESL design take advantage of the massive infrastructure of RTL tools and existing RTL IP? How would an ESL-to-RTL flow impact the IP industry? How can organizations utilize ESL today and what should they look for in the future? This panel of industry experts will address these questions, discuss how their organizations manage the gap between ESL and RTL methodologies, and map the technologies that hold the most promise for crossing the ESL-to-RTL divide.

Specific topics addressed in this panel:

• How should ESL bridge with RTL?
• What conclusions can we draw from RTL-to-gate evolution when looking at ESL-to-RTL evolution?
• What is the status of high-level synthesis and what can we really expect of it?
• Which design attributes are critical to be bridged across to RTL: IP development and reuse, functionality, testbench reuse, formal verification, hardware/software integration, timing analysis, power estimation?
• What does the bridge enable in a multi-processor chip development?
• How do two languages - SystemC and SystemVerilog – cooperate in the flow?
• How can TLM be practically linked to RTL?
• Can software be efficiently segmented accordingly (ESL vs. RTL)?
• What does the software development flow look like when the ESL-to-RTL bridge is established? What will be the benefit to the software designer of such a bridge?
• Which enabling technologies are needed to bridge the gap between ESL and RTL? What are the priorities?

Panel Moderator

• Peggy Aycinena, Editor of EDA Confidential

Panelists

• ARM: Dr. John Goodenough, Director of Design Technology
• CoWare: Eshel Haritan, Vice President of Engineering
• Mentor Graphics: Simon Bloch, General Manager, Design Creation & Synthesis Division
• Samsung: Dr. Joonhwan Yi, Senior Engineer, ESL (Electronic System Level) Technology Part Leader
• STMicroelectronics: Dr. Laurent Ducousso, R&D manager, Home Entertainment & Displays Group