Mentor.com :: Electronic System Level Design Resources

Industry Article:Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge

Thu, 01 Dec 2011 08:00:00 GMT

Energy Vs. Power: Energy, Power Optimization Is A System-Level Challenge

Industry Article:System Performance Analysis and Software Optimization Using a TLM Virtual Platform

Tue, 22 Nov 2011 08:00:00 GMT

System Performance Analysis and Software Optimization Using a TLM Virtual Platform

News Article:Mentor Graphics Vista ESL Platform Takes Center Stage in Mentor’s ESL Strategy with Expanded Functionality

Wed, 07 Sep 2011 13:00:00 GMT

WILSONVILLE, Ore., Sept. 7, 2011 - Mentor Graphics Corporation today announced it has expanded the Vista™ ESL Platform to address the needs for Virtual Prototyping for early software development. In addition, the Vista ESL platform’s integration with Catapult C, sharing common TLM modeling style for Virtual prototyping and HLS-based hardware implementation, has been strengthened with the Mentor® partnership with Calypto. The Vista ESL platform is the center point of the Mentor comprehensive ESL strategy, a strategy that has extended the boundaries of ESL technologies by addressing a broad range of electronic system design, virtual prototyping, hardware realization, software realization, and TLM-to-RTL verification and model reuse challenges.

Technology Overview:9th ESL Symposium Panel Discussion at DAC 2011

Fri, 08 Jul 2011 13:00:00 GMT

Executives from Intel, ARM, Freescale, ST and Mentor will examine the industry-wide move to ESL by highlighting the views and experiences of executives from leading semiconductor, IP and EDA companies.

Video is split into chapters for easy viewing.

White Paper:Embedded System Power Consumption: A Software or Hardware Issue?

Tue, 21 Jun 2011 07:00:00 GMT

The power consumption of devices and the issues around designing for low power are hot topics at this time. This paper looks at the issues from a system-wide perspective and gives guidance on design strategies that encompass both hardware and software development.

Blog Post:Mentor ESL in TSMC Reference Flow 12

Thomas Bollaert — Tue, 07 Jun 2011 04:52:25 GMT

One year ago, I was writing about the inclusion of Mentor ESL in the TSMC Reference Flow 11, and why the endorsement of system-level design and high-level synthesis by the world’s leading foundry was a telling sign of maturity for ESL. Since this first major milestone, TSMC and Mentor haven’t remained idle, on the contrary. Both parties teamed-up to take this first ESL flow to a whole new

Blog Post:48th DAC - Gary’s Magic Formula

Thomas Bollaert — Tue, 07 Jun 2011 01:16:07 GMT

Last night, in his traditional DAC-opening presentation, Gary Smith addressed the crowd with a loud and clear message about the cost of doing hardware design. Design costs are steadily increasing and this is draining life and blood out of the industry. When chip design costs reach $25M, VCs stop funding start-ups. When costs reach $50M, continued Gary Smith, even IDMs struggle to afford ASIC developments. So

News Article:Mentor Graphics Announces Common Embedded Software Development Platform for any Stage of Development from Virtual Prototypes to Hardware Emulation and Boards

Mon, 06 Jun 2011 10:00:00 GMT

DESIGN AUTOMATION CONFERENCE, San Diego, Calif., June 6, 2011 - Mentor Graphics Corporation today announced a unified embedded software debugging platform, from pre-silicon to final product, based on the integration of the Mentor® Embedded Sourcery™ CodeBench embedded software development tools with Mentor’s leading electronic system level (ESL), verification, and hardware emulation products. These include the Mentor Graphics® Vista™ Virtual Prototyping product, Veloce® hardware emulator, prototype target boards, and end products or any combination thereof. The new common platform, being shown at the Mentor booth #1542 at DAC, enables embedded software developers to access technology data from hardware design tools without leaving their native embedded software environment.

News Article:Mentor Graphics Forges TLM Synthesis Link Between Hardware Implementation and Virtual Prototyping

Tue, 31 May 2011 13:00:00 GMT

WILSONVILLE, Ore., May 31, 2011—Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Catapult® C high-level synthesis tool now supports the synthesis of transaction level models (TLMs). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista™ platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms.

On-demand Web Seminar:Saving verification time using TLM modeling

Tue, 17 May 2011 22:55:30 GMT

Today’s electronic systems embed one or more processors (with software!), bus, cache as well as more and more algorithm mapped in hardware in order to cope with performance requirements.

Validating and verifying the complete system is becoming a real challenge both in term of fonctionnality but also performance and power consumption.