High Level Synthesis

Moving Beyond Hand-Coded RTL Methodologies

Ever increasing design size and complexity have pushed traditional RTL methodologies to their limits. Design requirements and time-to-market pressures are combining to make it impossible for designers to find optimal RTL implementations within their allotted schedule. High-level synthesis reduces manual effort required to produce RTL, and enables designers to avoid syntax errors common in traditional methodologies. With high-level synthesis, designers are able to:

• Achieve 10-100x improvement in productivity
• Reduce number of hand-coded design errors
• Rapidly explore multiple architectural implementations

Products & Solutions

• Catapult Synthesis
  
  Catapult is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements.
• Catapult Library Builder
  
  Catapult™ Library Builder is a stand-alone tool that provides an easy and intuitive environment to generate and analyze libraries for Catapult Synthesis.