High Level Synthesis
High Level Synthesis reduces the manual effort required to create and completely verify synthesizable RTL code. Design size and complexity continue to push traditional RTL design and verification methodologies to their limits.
Improve Productivity
No longer can design teams double in size in order to design and verify twice the number of gates. Adding more engineers, irrespective of cost, to a project will no longer result in linear productivity gains. Product requirements and time-to-market pressures now make it impossible for designers to find and verify optimal RTL implementations within their allotted schedules. By leveraging the ANSI C++ and SystemC languages with the power of class-based design reuse and templates, designers become considerably more productive.
High Level Synthesis Technology Delivers:
- Significant reduction in validation and verification effort and time
- 10x to 100x improvement in your total “Time to Verified Gates” delivery
See our customer success stories for more details - An ability to quickly explore multiple architectural implementations and trade-offs
- Elimination of human errors introduced by misunderstandings during manual RTL coding
Catapult C Synthesis
Full-Chip High-Level Synthesis
Catapult is a High Level Synthesis tool for ASIC and FPGA hardware designers of wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Learn More About Catapult C Synthesis
High Level Synthesis Applications
Video & Image Processing Solutions
Video and image processing designs present an interesting set of algorithm modeling, design, and verification challenges, frequently centered around line buffers, windowing and other architectural bandwidth challenges. Catapult C Synthesis leverages a C++ based bit-accurate data type language entry as well as the SystemC language to enable rapid validation of algorithm and system architecture concepts.
Video
- SDTV and HDTV
- Compression and decompression
- Filtering, scaling and optimization
Imaging
- Medical Imaging - MRI, ultrasound
- Radar processing
- Machine vision
- Printer imaging
Broadband Wireless Solutions
Broadband wireless designs present an interesting set of algorithm modeling, design, and verification challenges. Catapult C Synthesis leverages a C++ based bit-accurate data type language entry as well as the SystemC language to enable rapid validation of algorithm and system architecture concepts.
- Network infrastructure
- Wireless handsets & basestations
- Cryptography
Low Power Solutions
Learn how Mentor can help you with your power consumption challenges, including how to balance power with existing requirements of system functionality, performance, and manufacturability.
The Unified Power Format (UPF) provides the backbone to our low power technologies so engineers can define power based architectures, create power aware strategies, and verify low power designs throughout the TLM to GDSII flow.
Datasheets
- Catapult C Synthesis (PDF, 2mb)
Toolbox
- TECHPUB: Boosting RTL Verification with High-Level Synthesis
- Technology Overview: High-Level Synthesis Primer
- On-demand Web Seminar: Hardware Designs Reuse Using C++ and High Level Synthesis
Contact Mentor Graphics
- Request Information or call toll free: 1-800-547-3000
From the Blogs
Take the High Road to Power-Optimized RTL
The latest edition of Chip Design Magazine features an insightful head-to-head discussion between Atrenta’s Kiran Vittal and Mentor’s Shawn McCloud. The topic: how to best achieve power-optimized RTL. Should…View Blog Post
Everything but Wives and Kids
Yes indeed, Apple’s unveiling of the iPad took center stage in the high-tech news last week. But as Steve Job’s show went on, another interesting piece of information hit the wire. According to analysts’…View Blog Post
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